Datasheet ADSP-21467, ADSP-21469 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | SHARC Processor |
| Páginas / Página | 76 / 2 — ADSP-21467/. ADSP-21469. TABLE OF CONTENTS. REVISION HISTORY. 3/13—Rev. A … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 2.3 Mb |
| Idioma del documento | Inglés |
ADSP-21467/. ADSP-21469. TABLE OF CONTENTS. REVISION HISTORY. 3/13—Rev. A to Rev. B
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ADSP-21467/ ADSP-21469 TABLE OF CONTENTS
Summary ... 1 ESD Sensitivity ... 23 General Description ... 3 Timing Specifications ... 23 Family Core Architecture .. 4 Test Conditions .. 62 Family Peripheral Architecture .. 7 Output Drive Currents ... 62 System Design .. 10 Capacitive Loading .. 63 Development Tools ... 11 Thermal Characteristics .. 65 Additional Information .. 12 CSP_BGA Ball Assignment—Automotive Models .. 67 Related Signal Chains .. 12 CSP_BGA Ball Assignment—Standard Models .. 70 Pin Function Descriptions ... 13 Outline Dimensions .. 73 Specifications .. 19 Surface-Mount Design .. 73 Operating Conditions .. 19 Automotive Products .. 74 Electrical Characteristics ... 20 Ordering Guide ... 74 Absolute Maximum Ratings .. 22 Package Information ... 22
REVISION HISTORY 3/13—Rev. A to Rev. B
Added BOOT_CFG2 signal to Table 62 Updated Development Tools .. 11 (CSP_BGA Ball Assignment) in CSP_BGA Ball Assignment— Standard Models .. 70 Revised termination description, AMI_MS0-1 pin description, Chip ID description, and V Added footnote to Table 62 DD_THD pin description in Pin Function Descriptions ... 13 (CSP_BGA Ball Assignment) in CSP_BGA Ball Assignment— Standard Models .. 70 Corrected parameter from IDD-INTYP to IDD_INT in Electrical Characteristics .. 20 Corrected ball assignments in Figure 61 in CSP_BGA Ball Assignment—Standard Models .. 70 Modified Total Power Dissipation .. 21 Added leaded model ADSP-21469BBC-3 to Corrected unit values for tCLKRST, tPLLRST, and tCORERST in Ordering Guide ... 74 Table 18 in Power-Up Sequencing ... 25 Modified note in Figure 8 in Clock Signals ... 26 Added footnote 3 to Table 31in AMI Read ... 35 Changed min value for parameter tDLACLK from tLCLK – 2 to 4 in Link Ports ... 39 Added Table 35 in Link Ports .. 39 Added Figure 24 in Link Ports .. 39 Relabeled table tile for Table 36 in Link Ports .. 39 Relabeled figure title for Figure 25 in Link Ports .. 39 Changed Max values in Table 46 in Pulse-Width Modulation (PWM) Generators .. 51 Added BOOT_CFG2 signal to Table 61 (CSP_BGA Ball Assignment) in CSP_BGA Ball Assignment— Automotive Models .. 67 Revised footnote for Table 61 (CSP_BGA Ball Assignment) in CSP_BGA Ball Assignment— Automotive Models .. 67 Corrected ball assignments in Figure 60 in CSP_BGA Ball Assignment—Automotive Models ... 67 Rev. B | Page 2 of 76 | March 2013 Document Outline Summary Table Of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth Nonsecured ROM ROM-Based Security Digital Transmission Content Protection Family Peripheral Architecture External Port External Memory SIMD Access to External Memory VISA and ISA Access to External Memory Shared External Memory DDR2 Support DDR2 DRAM Controller Asynchronous Memory Controller External Port Throughput Link Ports MediaLB Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral Interface UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA IIR Accelerator FFT Accelerator FIR Accelerator System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing AMI Read AMI Write Shared Memory Bus Request Link Ports Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation (PWM) Generators S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Test Conditions Output Drive Currents Capacitive Loading Thermal Characteristics Thermal Diode CSP_BGA Ball Assignment—Automotive Models CSP_BGA Ball Assignment—Standard Models Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
ADSP-21467/ ADSP-21469 TABLE OF CONTENTS
Summary ... 1 ESD Sensitivity ... 23 General Description ... 3 Timing Specifications ... 23 Family Core Architecture .. 4 Test Conditions .. 62 Family Peripheral Architecture .. 7 Output Drive Currents ... 62 System Design .. 10 Capacitive Loading .. 63 Development Tools ... 11 Thermal Characteristics .. 65 Additional Information .. 12 CSP_BGA Ball Assignment—Automotive Models .. 67 Related Signal Chains .. 12 CSP_BGA Ball Assignment—Standard Models .. 70 Pin Function Descriptions ... 13 Outline Dimensions .. 73 Specifications .. 19 Surface-Mount Design .. 73 Operating Conditions .. 19 Automotive Products .. 74 Electrical Characteristics ... 20 Ordering Guide ... 74 Absolute Maximum Ratings .. 22 Package Information ... 22
REVISION HISTORY 3/13—Rev. A to Rev. B
Added BOOT_CFG2 signal to Table 62 Updated Development Tools .. 11 (CSP_BGA Ball Assignment) in CSP_BGA Ball Assignment— Standard Models .. 70 Revised termination description, AMI_MS0-1 pin description, Chip ID description, and V Added footnote to Table 62 DD_THD pin description in Pin Function Descriptions ... 13 (CSP_BGA Ball Assignment) in CSP_BGA Ball Assignment— Standard Models .. 70 Corrected parameter from IDD-INTYP to IDD_INT in Electrical Characteristics .. 20 Corrected ball assignments in Figure 61 in CSP_BGA Ball Assignment—Standard Models .. 70 Modified Total Power Dissipation .. 21 Added leaded model ADSP-21469BBC-3 to Corrected unit values for tCLKRST, tPLLRST, and tCORERST in Ordering Guide ... 74 Table 18 in Power-Up Sequencing ... 25 Modified note in Figure 8 in Clock Signals ... 26 Added footnote 3 to Table 31in AMI Read ... 35 Changed min value for parameter tDLACLK from tLCLK – 2 to 4 in Link Ports ... 39 Added Table 35 in Link Ports .. 39 Added Figure 24 in Link Ports .. 39 Relabeled table tile for Table 36 in Link Ports .. 39 Relabeled figure title for Figure 25 in Link Ports .. 39 Changed Max values in Table 46 in Pulse-Width Modulation (PWM) Generators .. 51 Added BOOT_CFG2 signal to Table 61 (CSP_BGA Ball Assignment) in CSP_BGA Ball Assignment— Automotive Models .. 67 Revised footnote for Table 61 (CSP_BGA Ball Assignment) in CSP_BGA Ball Assignment— Automotive Models .. 67 Corrected ball assignments in Figure 60 in CSP_BGA Ball Assignment—Automotive Models ... 67 Rev. B | Page 2 of 76 | March 2013 Document Outline Summary Table Of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth Nonsecured ROM ROM-Based Security Digital Transmission Content Protection Family Peripheral Architecture External Port External Memory SIMD Access to External Memory VISA and ISA Access to External Memory Shared External Memory DDR2 Support DDR2 DRAM Controller Asynchronous Memory Controller External Port Throughput Link Ports MediaLB Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral Interface UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA IIR Accelerator FFT Accelerator FIR Accelerator System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing AMI Read AMI Write Shared Memory Bus Request Link Ports Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation (PWM) Generators S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Test Conditions Output Drive Currents Capacitive Loading Thermal Characteristics Thermal Diode CSP_BGA Ball Assignment—Automotive Models CSP_BGA Ball Assignment—Standard Models Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide