Datasheet ADSP-21467, ADSP-21469 (Analog Devices) - 3

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ADSP-21467 /ADSP-21469 GENERAL DESCRIPTION
The ADSP-21467/ADSP-21469 SHARC® processors are mem-
Table 2. SHARC Family Features (Continued)
bers of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source
Feature ADSP-21467 ADSP-21469
code compatible with the ADSP-2126x, ADSP-2136x, SPI 2 ADSP-2137x, and ADSP-2116x DSPs, as well as with first TWI Yes generation ADSP-2106x SHARC processors in SISD (single- SRC Performance –128 dB instruction, single-data) mode. These 32-bit/40-bit floating- Package 324-Ball CSP_BGA point processors are optimized for high performance audio applications with their large on-chip SRAM, multiple internal 1 Factory programmed ROM includes: Dolby AC-3 5.1 Decode, Dolby Pro Logic IIx, buses to eliminate I/O bottlenecks, and an innovative digital Dolby Intelligent Mixer (eMix), Dolby Volume postprocessor, Dolby Headphone v2, DTS Neo:6 and Decode, DTS 5.1 Decode (96/24), Math Tables/Twiddle applications/peripheral interfaces (DAI/DPI). Factors/256 and 512 FFT, and ASRC. Please visit www.analog.com for complete Table 1 shows performance benchmarks for the processor, and product information and availability. 2 Contact your local Analog Devices sales office for more information regarding Table 2 shows the product’s features. availability of ADSP-21467/ADSP-21469 processors which support DTCP.
Table 1. Processor Benchmarks
Figure 1 on Page 1 shows the two clock domains that make up the processor. The core clock domain contains the following
Speed
features:
Benchmark Algorithm (at 450 MHz)
1024 Point Complex FFT (Radix 4, with Reversal) 20.44 s • Two processing elements (PEx, PEy), each of which com- prises an ALU, multiplier, shifter, and data register file FIR Filter (Per Tap)1 1.11 ns IIR Filter (Per Biquad)1 4.43 ns • Data address generators (DAG1, DAG2) Matrix Multiply (Pipelined) • Program sequencer with instruction cache [3 × 3] × [3 × 1] 10.0 ns • One periodic interval timer with pinout [4 × 4] × [4 × 1] 17.78 ns • PM and DM buses capable of supporting 2 × 64-bit data Divide (y/x) 6.67 ns transfers between memory and the core at every core pro- Inverse Square Root 10.0 ns cessor cycle 1 Assumes two files in multichannel SIMD mode • On-chip SRAM (5 Mbits) • On-chip mask-programmable ROM (4 Mbits)
Table 2. SHARC Family Features
• JTAG test access port for emulation and boundary scan.
Feature ADSP-21467 ADSP-21469
The JTAG provides software debug through user break- Maximum Frequency 450 MHz points which allows flexible exception handling. RAM 5 Mbits Figure 1 on Page 1 also shows the peripheral clock domain (also ROM 4 Mbits N/A known as the I/O processor) which contains the following Audio Decoders in ROM1 Yes No features: DTCP Hardware Accelerator2 No • IOD0 (periphera l DMA) and IOD1 (external port DMA) Pulse-Width Modulation Yes buses for 32-bit data transfers S/PDIF Yes • Peripheral and external port buses for core connection DDR2 Memory Interface Yes • External port with an AMI and DDR2 controller DDR2 Memory Bus Width 16 Bits • 4 units for PWM control Shared DDR2 External Memory Yes • 1 MTM unit for internal-to-internal memory transfers Direct DMA from SPORTs to • Digital applications interface that includes four precision External Memory Yes clock generators (PCG), an input data port (IDP) for serial FIR, IIR, FFT Accelerator Yes and parallel interconnect, an S/PDIF receiver/transmitter, MLB Interface Automotive Models Only four asynchronous sample rate converters, eight serial IDP Yes ports, a flexible signal routing unit (DAI SRU). Serial Ports 8 • Digital peripheral interface that includes two timers, a 2- DAI (SRU)/DPI (SRU2) 20/14 pins wire interface, one UART, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG) and a flexible UART 1 signal routing unit (DPI SRU). Link Ports 2 AMI Interface with 8-Bit Support Yes Rev. B | Page 3 of 76 | March 2013 Document Outline Summary Table Of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth Nonsecured ROM ROM-Based Security Digital Transmission Content Protection Family Peripheral Architecture External Port External Memory SIMD Access to External Memory VISA and ISA Access to External Memory Shared External Memory DDR2 Support DDR2 DRAM Controller Asynchronous Memory Controller External Port Throughput Link Ports MediaLB Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral Interface UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA IIR Accelerator FFT Accelerator FIR Accelerator System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing AMI Read AMI Write Shared Memory Bus Request Link Ports Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation (PWM) Generators S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Test Conditions Output Drive Currents Capacitive Loading Thermal Characteristics Thermal Diode CSP_BGA Ball Assignment—Automotive Models CSP_BGA Ball Assignment—Standard Models Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide