Datasheet ADSP-21467, ADSP-21469 (Analog Devices) - 5

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ADSP-21467 /ADSP-21469
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JTAG FLAG TIMER INTERRUPT CACHE SIMD Core PM ADDRESS 24 DMD/PMD 64 5 STAGE PROGRAM SEQUENCER PM DATA 48 DAG1 DAG2 16 × 32 16 × 32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 USTAT PM DATA 64 4 × 32-BIT PX DM DATA 64 64-BIT RF DATA RF SWAP MULTIPLIER SHIFTER ALU Rx/Fx Sx/SFx ALU SHIFTER MULTIPLIER PEx PEy 16 × 40-BIT 16 × 40-BIT MRF MRB MSB MSF 80-BIT 80-BIT ASTATx ASTATy 80-BIT 80-BIT STYKx STYKy
Figure 2. SHARC Core Block Diagram
Flexible Instruction Set On-Chip Memory
The 48-bit instruction word accommodates a variety of parallel The processors contain 5 Mbits of internal RAM. Each block operations for concise programming. For example, the can be configured for different combinations of code and data processor can conditionally execute a multiply, an add, and a storage (see Table 4). Each memory block supports single-cycle, subtract in both processing elements while branching and fetch- independent accesses by the core processor and I/O processor. ing up to four 32-bit values from memory—all in a single The memory architecture, in combination with its separate on- instruction. chip buses, allows two data transfers from the core and one from the I/O processor in a single cycle.
Variable Instruction Set Architecture (VISA)
The processor’s SRAM can be configured as a maximum of In addition to supporting the standard 48-bit instructions from 160k words of 32-bit data, 320k words of 16-bit data, 106.7k previous SHARC processors, the processors support new words of 48-bit instructions (or 40-bit data), or combinations of instructions of 16 and 32 bits. This feature, called Variable different word sizes up to 5 Mbits. All of the memory can be Instruction Set Architecture (VISA), drops redundant/unused accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit bits within the 48-bit instruction to create more efficient and floating-point storage format is supported that effectively compact code. The program sequencer supports fetching these doubles the amount of data that may be stored on-chip. Conver- 16-bit and 32-bit instructions from both internal and external sion between the 32-bit floating-point and 16-bit floating-point DDR2 memory. Source modules need to be built using the formats is performed in a single instruction. While each VISA option in order to allow code generation tools to create memory block can store combinations of code and data, these more efficient opcodes. accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Rev. B | Page 5 of 76 | March 2013 Document Outline Summary Table Of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth Nonsecured ROM ROM-Based Security Digital Transmission Content Protection Family Peripheral Architecture External Port External Memory SIMD Access to External Memory VISA and ISA Access to External Memory Shared External Memory DDR2 Support DDR2 DRAM Controller Asynchronous Memory Controller External Port Throughput Link Ports MediaLB Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral Interface UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA IIR Accelerator FFT Accelerator FIR Accelerator System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing AMI Read AMI Write Shared Memory Bus Request Link Ports Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation (PWM) Generators S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Test Conditions Output Drive Currents Capacitive Loading Thermal Characteristics Thermal Diode CSP_BGA Ball Assignment—Automotive Models CSP_BGA Ball Assignment—Standard Models Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide