Datasheet ADSP-21467, ADSP-21469 (Analog Devices)

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SHARC Processor ADSP-21467 /ADSP-21469 SUMMARY High performance 32-bit/40-bit floating-point processor Available with unique audiocentric peripherals such as the optimized for high performance audio processing digital applications interface, DTCP (digital transmission Single-instruction, multiple-data (SIMD) computational content protection protocol), serial ports, precision clock architecture generators, S/PDIF transceiver, asynchronous sample rate 5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM converters, input data port, and more. Up to 450 MHz operating frequency For complete ordering information, see Ordering Guide on Qualified for automotive applications, see Automotive Prod- Page 74 ucts on Page 74 Code compatible with all other members of the SHARC family INTERNAL MEMORY SIMD CORE BLOCK 0 BLOCK 1 BLOCK 2 BLOCK 3 RAM/ROM RAM/ROM RAM RAM INSTRUCTION 5 STAGE CACHE SEQUENCER B0D B1D B2D B3D 64-BIT 64-BIT 64-BIT 64-BIT
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DAG1/2 TIMER DMD DMD 64-BIT 64-BIT PEX PEY CORE BUS INTERNAL MEMORY INTERFACE CROSS BAR PMD PMD 64-BIT 64-BIT FLAGx/IRQx/ THERMAL IOD0 32-BIT EPD BUS 64-BIT JTAG TMREXP DIODE IOD1 32-BIT PERIPHERAL BUS 32-BIT IOD0 BUS FFT DTCP/ FIR MTM PERIPHERAL BUS IIR EP SPEP BUS LINK CORE PCG TIMER S/PDIF PCG ASRC PDAP/ SPORT CORE PWM TWI SPI/B DDR2 UART IDP MLB PORT AMI FLAGS C-D 1-0 TX/RX A-D 3-0 7-0 FLAGS 3-0 CTL 7-0 1-0 DPI ROUTING/PINS DAI ROUTING/PINS EXTERNAL PORT PIN MUX EXTERNAL PORT DPI PERIPHERALS DAI PERIPHERALS PERIPHERALS
Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
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Document Outline Summary Table Of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth Nonsecured ROM ROM-Based Security Digital Transmission Content Protection Family Peripheral Architecture External Port External Memory SIMD Access to External Memory VISA and ISA Access to External Memory Shared External Memory DDR2 Support DDR2 DRAM Controller Asynchronous Memory Controller External Port Throughput Link Ports MediaLB Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral Interface UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA IIR Accelerator FFT Accelerator FIR Accelerator System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing AMI Read AMI Write Shared Memory Bus Request Link Ports Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation (PWM) Generators S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Test Conditions Output Drive Currents Capacitive Loading Thermal Characteristics Thermal Diode CSP_BGA Ball Assignment—Automotive Models CSP_BGA Ball Assignment—Standard Models Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide