Datasheet ADSP-21467, ADSP-21469 (Analog Devices) - 10

link to page 10 link to page 10 link to page 11 link to page 11
ADSP-21467/ ADSP-21469 DMA Controller SYSTEM DESIGN
The DMA controller allows data transfers without processor The following sections provide an introduction to system design intervention. The DMA controller operates independently and options and power supply issues. invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program
Program Booting
instructions. DMA transfers can occur between the processor’s The internal memory boots at system power-up from an 8-bit internal memory and its serial ports, the SPI-compatible (serial EPROM via the external port, link port, an SPI master, or an SPI peripheral interface) ports, the IDP (input data port), the paral- slave. Booting is determined by the boot configuration lel data acquisition port (PDAP), or the UART. (BOOTCFG2–0) pins in Table 8. Up to 67 channels of DMA are available as shown in Table 7. Programs can be downloaded to the processor using DMA
Table 8. Boot Mode Selection
transfers. Other DMA features include interrupt generation
BOOTCFG2–0 Booting Mode
upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. 000 SPI Slave Boot 001 SPI Master Boot
Delay Line DMA
010 AMI Boot (for 8-bit Flash boot) Delay line DMA allows processor reads and writes to external 011 No boot occurs, processor executes from delay line buffers (and hence to external memory) with limited internal ROM after reset core interaction. 100 Link Port 0 Boot
Scatter/Gather DMA
101 Reserved Scatter/gather DMA allows DMA reads/writes to/from non- contiguous memory blocks. The running reset feature allows programs to perform a reset of the processor core and peripherals, without resetting the PLL
Table 7. DMA Channels
and DDR2 DRAM controller or performing a boot. The function of the RESETOUT pin also acts as the input for initiat-
Peripheral DMA Channels
ing a running reset. For more information, see the ADSP-214xx SPORTs 16 SHARC Processor Hardware Reference. IDP/PDAP 8
Power Supplies
SPI 2 The processors have separate power supply connections UART 2 for the internal (VDD_INT), external (VDD_EXT), and analog External Port 2 (VDD_A) power supplies. The internal and analog supplies must Link Port 2 meet the VDD_INT specifications. The external supply must meet Accelerators 2 the VDD_EXT specification. All external supply pins must be con- nected to the same power supply. Memory-to-Memory 2 MLB1 31 Note that the analog power supply pin (VDD_A) powers the pro- 1 cessor’s internal clock generator PLL. To produce a stable clock, Automotive models only. it is recommended that PCB designs use an external filter circuit for the VDD_A pin. Place the filter components as close as possi-
IIR Accelerator
ble to the VDD_A/AGND pins. For an example circuit, see The IIR (infinite impulse response) accelerator consists of a Figure 3. (A recommended ferrite chip is the muRata 1440 word coefficient memory for storage of biquad coeffi- BLM18AG102SN1D). cients, a data memory for storing the intermediate data, and one To reduce noise coupling, the PCB should use a parallel pair of MAC unit. A controller manages the accelerator. The IIR accel- power and ground planes for VDD_INT and GND. Use wide erator runs at the peripheral clock frequency. traces to connect the bypass capacitors to the analog power
FFT Accelerator
(VDD_A) and ground (AGND) pins. Note that the VDD_A and AGND pins specified in Figure 3 are inputs to the processor and FFT accelerator implements radix-2 complex/real input, com- not the analog ground plane on the board—the AGND pin plex output FFT with no core intervention. The FFT accelerator should connect directly to digital ground (GND) at the chip. runs at the peripheral clock frequency.
Target Board JTAG Emulator Connector FIR Accelerator
Analog Devices DSP Tools product line of JTAG emulators uses The FIR (finite impulse response) accelerator consists of a 1024 the IEEE 1149.1 JTAG test access port of the processor to moni- word coefficient memory, a 1024 word deep delay line for the tor and control the target board processor during emulation. data, and four MAC units. A controller manages the accelerator. Analog Devices DSP Tools product line of JTAG emulators pro- The FIR accelerator runs at the peripheral clock frequency. vides emulation at full processor speed, allowing inspection and Rev. B | Page 10 of 76 | March 2013 Document Outline Summary Table Of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth Nonsecured ROM ROM-Based Security Digital Transmission Content Protection Family Peripheral Architecture External Port External Memory SIMD Access to External Memory VISA and ISA Access to External Memory Shared External Memory DDR2 Support DDR2 DRAM Controller Asynchronous Memory Controller External Port Throughput Link Ports MediaLB Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral Interface UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA IIR Accelerator FFT Accelerator FIR Accelerator System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing AMI Read AMI Write Shared Memory Bus Request Link Ports Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation (PWM) Generators S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Test Conditions Output Drive Currents Capacitive Loading Thermal Characteristics Thermal Diode CSP_BGA Ball Assignment—Automotive Models CSP_BGA Ball Assignment—Standard Models Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide