Datasheet AD9225 (Analog Devices) - 5

FabricanteAnalog Devices
Descripción12-Bit , 25 MSPS Monolithic A/D Converter
Páginas / Página26 / 5 — AD9225. ABSOLUTE MAXIMUM RATINGS*. With. Pin Name. Respect to. Min. Max. …
RevisiónC
Formato / tamaño de archivoPDF / 1.0 Mb
Idioma del documentoInglés

AD9225. ABSOLUTE MAXIMUM RATINGS*. With. Pin Name. Respect to. Min. Max. Unit. PIN CONFIGURATION. ANALOG. INPUT. 28-Lead SOIC and SSOP. tCL

AD9225 ABSOLUTE MAXIMUM RATINGS* With Pin Name Respect to Min Max Unit PIN CONFIGURATION ANALOG INPUT 28-Lead SOIC and SSOP tCL

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AD9225 ABSOLUTE MAXIMUM RATINGS* With Pin Name Respect to Min Max Unit
AVDD AVSS –0.3 +6.5 V DRVDD DRVSS –0.3 +6.5 V AVSS DRVSS –0.3 +0.3 V AVDD DRVDD –6.5 +6.5 V REFCOM AVSS –0.3 +0.3 V CLK AVSS –0.3 AVDD + 0.3 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V VINA, VINB AVSS –0.3 AVDD + 0.3 V VREF AVSS –0.3 AVDD + 0.3 V SENSE AVSS –0.3 AVDD + 0.3 V CAPB, CAPT AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 ∞C Storage Temperature –65 +150 ∞C Lead Temperature (10 sec) 300 ∞C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
S1 S2 PIN CONFIGURATION ANALOG t S4 C INPUT t S3 28-Lead SOIC and SSOP CH tCL INPUT CLOCK CLK 1 DRVDD t 28 OD (LSB) BIT 12 2 27 DRVSS DATA DATA 1 OUTPUT BIT 11 3 26 AVDD BIT 10 4 25 AVSS
Figure 1. Timing Diagram
BIT 9 5 24 VINB BIT 8 6 23 VINA AD9225 BIT 7 7 TOP VIEW 22 CML (Not to Scale) BIT 6 8 21 CAPT BIT 5 9 20 CAPB BIT 4 10 19 REFCOM BIT 3 11 18 VREF BIT 2 12 17 SENSE (MSB) BIT 1 13 16 AVSS OTR 14 15 AVDD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9225 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– Rev. C Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity (INL) Differential Nonlinearity (DNL, No Missing Codes) Zero Error Gain Error Temperature Drift Power Supply Rejection Aperture Jitter Aperture Delay Signal-to-Noise and Distortion Ratio (S/N+D, SINAD) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) TYPICAL PERFORMANCE CHARACTERISTICS INTRODUCTION ANALOG INPUT AND REFERENCE OVERVIEW ANALOG INPUT OPERATION REFERENCE OPERATION DRIVING THE ANALOG INPUTS SINGLE-ENDED MODE OF OPERATION DC COUPLING AND INTERFACE ISSUES Simple Op Amp Buffer Op Amp with DC Level Shifting AC COUPLING AND INTERFACE ISSUES Simple AC Interface Alternative AC Interface OP AMP SELECTION GUIDE DIFFERENTIAL MODE OF OPERATION REFERENCE CONFIGURATIONS USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 3 VREF Range Resistor Programmable Reference USING AN EXTERNAL REFERENCE Variable Input Span with VCM = 2.5 V Single-Ended Input with 0 to 2 ¥ VREF Range DIGITAL INPUTS AND OUTPUTS Digital Outputs Out-Of-Range (OTR) Digital Output Driver Considerations (DRVDD) Clock Input and Considerations Direct IF Down Conversion Using the AD9225 GROUNDING AND DECOUPLING Analog and Digital Grounding Analog and Digital Driver Supply Decoupling OUTLINE DIMENSIONS Ordering Guide REVISION HISTORY