Datasheet AD9225 (Analog Devices) - 10

AD9225
Due to the high degree of symmetry within the SHA topology, a
VCC
significant improvement in distortion performance for differen-
AD9225 RS
tial input signals with frequencies up to and beyond Nyquist can
VINA R
be realized. This inherent symmetry provides excellent cancella-
S VINB
tion of both common-mode distortion and noise. Also, the
VEE
required input signal voltage span is reduced by a half, which
VREF
further reduces the degree of R
10 F 0.1 F
ON modulation and its effects
SENSE
on distortion.
REFCOM
The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest Figure 4. Series Resistor Isolates Switched Capacitor input signal voltage span (i.e., 4 V input span) and matched SHA Input from Op Amp. Matching Resistors Improve input impedance for VINA and VINB. Only a slight degrada- SNR Performance. tion in dc linearity performance exists between the 2 V and 4 V input spans. The optimum size of this resistor is dependent on several fac- tors, which include the ADC sampling rate, the selected op Referring to Figure 3, the differential SHA is implemented amp, and the particular application. In most applications, a using a switched capacitor topology. Its input impedance and its 30 W to 100 W resistor is sufficient. However, some applica- switching effects on the input drive source should be considered tions may require a larger resistor value to reduce the noise in order to maximize the converter’s performance. The combi- bandwidth or possibly to limit the fault current in an overvolt- nation of the pin capacitance, CPIN, parasitic capacitance, CPAR, age condition. Other applications may require a larger resistor and the sampling capacitance, CS, is typically less than 5 pF. value as part of an antialiasing filter. In any case, since the THD When the SHA goes into track mode, the input source must performance is dependent on the series resistance and the above charge or discharge the voltage stored on CS to the new input mentioned factors, optimizing this resistor value for a given voltage. This action of charging and discharging CS, averaged application is encouraged. over a period of time and for a given sampling frequency, fS, makes the input impedance appear to have a benign resistive The source impedance driving VINA and VINB should be component. However, if this action is analyzed within a sampling matched. Failure to provide that matching will result in degra- period (i.e., T = 1/f dation of the AD9225’s superb SNR, THD, and SFDR. S), the input impedance is dynamic and therefore certain precautions on the input drive source should For noise sensitive applications, the very high bandwidth of the be observed. AD9225 may be detrimental. The addition of a series resistor The resistive component to the input impedance can be com- and/or shunt capacitor can help limit the wideband noise at the puted by calculating the average charge that gets drawn by C ADC’s input by forming a low-pass filter. Note, however, that H from the input drive source. It can be shown that if C the combination of this series resistance with the equivalent S is al- lowed to fully charge up to the input voltage before switches input capacitance of the AD9225 should be evaluated for Q those time domain applications that are sensitive to the input S1 are opened, then the average current into the input would be the same as it would if there were a resistor of 1/(C signal’s absolute settling time. In applications where harmonic S fS) Ohms connected between the inputs. This means that the input im- distortion is not a primary concern, the series resistance may be pedance is inversely proportional to the converter’s sample selected in combination with the SHA’s nominal 10 pF of input rate. Since C capacitance to set the filter’s 3 dB cutoff frequency. S is only 5 pF, this resistive component is typically much larger than that of the drive source (i.e., 8 kW at fS = A better method of reducing the noise bandwidth, while possi- 25 MSPS). bly establishing a real pole for an antialiasing filter, is to add The SHA’s input impedance over a sampling period appears as some additional shunt capacitance between the input (i.e., a dynamic input impedance to the input drive source. When the VINA and/or VINB) and analog ground. Since this additional SHA goes into the track mode, the input source ideally should shunt capacitance combines with the equivalent input capaci- provide the charging current through R tance of the AD9225, a lower series resistance can be selected to ON of switch QS1 in an exponential manner. The requirement of exponential charging establish the filter’s cutoff frequency while not degrading the means that the most common input source, an op amp, must distortion performance of the device. The shunt capacitance exhibit a source impedance that is both low and resistive up to also acts like a charge reservoir, sinking or sourcing the addi- and beyond the sampling frequency. tional charge required by the hold capacitor, CH, and further reducing current transients seen at the op amp’s output. The output impedance of an op amp can be modeled with a series inductor and resistor. When a capacitive load is switched The effect of this increased capacitive load on the op amp driv- onto the output of the op amp, the output will momentarily ing the AD9225 should be evaluated. To optimize performance drop due to its effective output impedance. As the output recov- when noise is the primary consideration, increase the shunt ers, ringing may occur. To remedy the situation, a series resistor capacitance as much as the transient response of the input signal can be inserted between the op amp and the SHA input as will allow. Increasing the capacitance too much may adversely shown in Figure 4. The series resistance helps isolate the op affect the op amp’s settling time, frequency response, and dis- amp from the switched capacitor load. tortion performance. Rev. C –9– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity (INL) Differential Nonlinearity (DNL, No Missing Codes) Zero Error Gain Error Temperature Drift Power Supply Rejection Aperture Jitter Aperture Delay Signal-to-Noise and Distortion Ratio (S/N+D, SINAD) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) TYPICAL PERFORMANCE CHARACTERISTICS INTRODUCTION ANALOG INPUT AND REFERENCE OVERVIEW ANALOG INPUT OPERATION REFERENCE OPERATION DRIVING THE ANALOG INPUTS SINGLE-ENDED MODE OF OPERATION DC COUPLING AND INTERFACE ISSUES Simple Op Amp Buffer Op Amp with DC Level Shifting AC COUPLING AND INTERFACE ISSUES Simple AC Interface Alternative AC Interface OP AMP SELECTION GUIDE DIFFERENTIAL MODE OF OPERATION REFERENCE CONFIGURATIONS USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 3 VREF Range Resistor Programmable Reference USING AN EXTERNAL REFERENCE Variable Input Span with VCM = 2.5 V Single-Ended Input with 0 to 2 ¥ VREF Range DIGITAL INPUTS AND OUTPUTS Digital Outputs Out-Of-Range (OTR) Digital Output Driver Considerations (DRVDD) Clock Input and Considerations Direct IF Down Conversion Using the AD9225 GROUNDING AND DECOUPLING Analog and Digital Grounding Analog and Digital Driver Supply Decoupling OUTLINE DIMENSIONS Ordering Guide REVISION HISTORY