Datasheet AD9225 (Analog Devices) - 9

AD9225 INTRODUCTION
the difference of the voltages applied at the VINA and VINB The AD9225 is a high performance, complete single-supply input pins. Therefore, the equation 12-bit ADC. The analog input range of the AD9225 is highly VCORE = VINA – VINB (1) flexible, allowing for both single-ended or differential inputs of varying amplitudes that can be ac-coupled or dc-coupled. defines the output of the differential input stage and provides the input to the ADC core. The AD9225 utilizes a four-stage pipeline architecture with a wideband input sample-and-hold amplifier (SHA) implemented The voltage, VCORE, must satisfy the condition on a cost-effective CMOS process. Each stage of the pipeline, –VREF £ VCORE £ VREF (2) excluding the last stage, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue where VREF is the voltage at the VREF pin. amplifier (MDAC). The residue amplifier amplifies the differ- While an infinite combination of VINA and VINB inputs exist ence between the reconstructed DAC output and the flash input that satisfy Equation 2, there is an additional limitation placed for the next stage in the pipeline. One bit of redundancy is used on the inputs by the power supply voltages of the AD9225. The in each of the stages to facilitate digital correction of flash errors. power supplies bound the valid operating range for VINA and The last stage simply consists of a flash ADC. VINB. The condition The pipeline architecture allows a greater throughput rate at the AVSS – 0.3 V < VINA < AVDD + 0.3 V (3) expense of pipeline delay or latency. This means that while the converter is capable of capturing a new input sample every clock AVSS – 0.3 V < VINB < AVDD + 0.3 V cycle, it actually takes three clock cycles for the conversion to where AVSS is nominally 0 V and AVDD is nominally 5 V, be fully processed and appear at the output. This latency is not defines this requirement. The range of valid inputs for VINA a concern in most applications. The digital output, together and VINB is any combination that satisfies both Equations with the out-of-range indicator (OTR), is latched into an 2 and 3. output buffer to drive the output pins. The output drivers of the AD9225 can be configured to interface with 5 V or 3.3 V For additional information showing the relationships among logic families. VINA, VINB, VREF, and the digital output of the AD9225, see Table IV. The AD9225 uses both edges of the clock in its internal timing circuitry (see Figure 1 and Specifications tables for exact timing Refer to Table I and Table II at the end of this section for a sum- requirements). The ADC samples the analog input on the rising mary of the various analog input and reference configurations. edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock), the input SHA is in
ANALOG INPUT OPERATION
the sample mode; during the clock high time it is in hold mode. Figure 3 shows the equivalent analog input of the AD9225, System disturbances just prior to the rising edge of the clock which consists of a differential sample-and-hold amplifier. The and/or excessive clock jitter may cause the input SHA to acquire differential input structure of the SHA is highly flexible, allow- the wrong value, and should be minimized. ing the devices to be easily configured for either a differential or single-ended input. The dc offset, or common-mode voltage, of the input(s) can be set to accommodate either single-supply or
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 2 is a simplified model of the AD9225. It highlights the dual-supply systems. Also, note that the analog inputs, VINA relationship between the analog inputs, VINA and VINB, and the and VINB, are interchangeable, with the exception that revers- reference voltage, VREF. Like the voltage applied to the top of ing the inputs to the VINA and VINB pins results in a polarity the resistor ladder in a flash ADC, the value VREF defines the inversion. maximum input voltage to the ADC core. The minimum input
CH
voltage to the ADC core is automatically defined to be –VREF.
QS2 C + AD9225 PIN Q CS VINA C S1 PAR +VREF VINA Q Q S1 H1 C V S CORE 12 ADC VINB CORE C – PIN Q C S2 PAR VINB –VREF CH
Figure 2. Equivalent Functional Input Circuit Figure 3. Simplified Input Circuit The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional The AD9225 has a wide input range. The input peaks may be flash converters. The input stage allows the user to easily config- moved to AVDD or AVSS before performance is compromised. ure the inputs for either single-ended operation or differential This allows for much greater flexibility when selecting single- operation. The A/D converter’s input structure allows the dc ended drive schemes. Op amps and ac coupling clamps can be offset of the input signal to be varied independently of the input set to available reference levels rather than be dictated according span of the converter. Specifically, the input to the ADC core is to what the ADC needs. –8– Rev. C Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity (INL) Differential Nonlinearity (DNL, No Missing Codes) Zero Error Gain Error Temperature Drift Power Supply Rejection Aperture Jitter Aperture Delay Signal-to-Noise and Distortion Ratio (S/N+D, SINAD) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) TYPICAL PERFORMANCE CHARACTERISTICS INTRODUCTION ANALOG INPUT AND REFERENCE OVERVIEW ANALOG INPUT OPERATION REFERENCE OPERATION DRIVING THE ANALOG INPUTS SINGLE-ENDED MODE OF OPERATION DC COUPLING AND INTERFACE ISSUES Simple Op Amp Buffer Op Amp with DC Level Shifting AC COUPLING AND INTERFACE ISSUES Simple AC Interface Alternative AC Interface OP AMP SELECTION GUIDE DIFFERENTIAL MODE OF OPERATION REFERENCE CONFIGURATIONS USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 3 VREF Range Resistor Programmable Reference USING AN EXTERNAL REFERENCE Variable Input Span with VCM = 2.5 V Single-Ended Input with 0 to 2 ¥ VREF Range DIGITAL INPUTS AND OUTPUTS Digital Outputs Out-Of-Range (OTR) Digital Output Driver Considerations (DRVDD) Clock Input and Considerations Direct IF Down Conversion Using the AD9225 GROUNDING AND DECOUPLING Analog and Digital Grounding Analog and Digital Driver Supply Decoupling OUTLINE DIMENSIONS Ordering Guide REVISION HISTORY