AD9225PIN FUNCTION DESCRIPTIONSPin NumberMnemonicDescription 1 CLK Clock Input Pin 2 BIT 12 Least Significant Data Bit (LSB) 3–12 BIT 11–2 Data Output Bit 13 BIT 1 Most Significant Data Bit (MSB) 14 OTR Out of Range 15, 26 AVDD 5 V Analog Supply 16, 25 AVSS Analog Ground 17 SENSE Reference Select 18 VREF Input Span Select (Reference I/O) 19 REFCOM Reference Common (AVSS) 20 CAPB Noise Reduction Pin 21 CAPT Noise Reduction Pin 22 CML Common-Mode Level (Midsupply) 23 VINA Analog Input Pin (+) 24 VINB Analog Input Pin (–) 27 DRVSS Digital Output Driver Ground 28 DRVDD 3 V to 5 V Digital Output Driver Supply TERMINOLOGYAperture DelayIntegral Nonlinearity (INL) Aperture delay is a measure of the sample-and-hold amplifier INL refers to the deviation of each individual code from a line (SHA) performance and is measured from the rising edge of the drawn from negative full scale through positive full scale. The clock input to when the input signal is held for conversion. point used as negative full scale occurs 1/2 LSB before the first Signal-to-Noise and Distortion Ratio (S/N+D, SINAD) code transition. Positive full scale is defined as a level 1 1/2 LSB S/N+D is the ratio of the rms value of the measured input beyond the last code transition. The deviation is measured from signal to the rms sum of all other spectral components below the middle of each particular code to the true straight line. the Nyquist frequency, including harmonics but excluding dc. Differential Nonlinearity (DNL, No Missing Codes) The value for S/N+D is expressed in decibels. An ideal ADC exhibits code transitions that are exactly 1 LSB Effective Number of Bits (ENOB) apart. DNL is the deviation from this ideal value. Guaranteed For a sine wave, SINAD can be expressed in terms of the num- no missing codes to 12-bit resolution indicates that all 4096 ber of bits. Using the following formula, codes, respectively, must be present over all operating ranges. N = (SINAD – 1.76)/6.02 Zero Error The major carry transition should occur for an analog value it is possible to get a measure of performance expressed as N, 1/2 LSB below VINA = VINB. Zero error is defined as the the effective number of bits. deviation of the actual transition from that point. The effective number of bits for a device for sine wave inputs at Gain Error a given input frequency can be calculated directly from its mea- The first code transition should occur at an analog value 1/2 LSB sured SINAD. above negative full scale. The last transition should occur at an Total Harmonic Distortion (THD) analog value 1 1/2 LSB below the nominal full scale. Gain error THD is the ratio of the rms sum of the first six harmonic com- is the deviation of the actual difference between first and last ponents to the rms value of the measured input signal and is code transitions and the ideal difference between first and last expressed as a percentage or in decibels. code transitions. Signal-to-Noise Ratio (SNR)Temperature Drift SNR is the ratio of the rms value of the measured input signal to The temperature drift for zero error and gain error specifies the the rms sum of all other spectral components below the Nyquist maximum change from the initial (25∞C) value to the value at frequency, excluding the first six harmonics and dc. The value TMIN or TMAX. for SNR is expressed in decibels. Power Supply RejectionSpurious-Free Dynamic Range (SFDR) The specification shows the maximum change in full scale from SFDR is the difference in dB between the rms amplitude of the the value with the supply at the minimum limit to the value with input signal and the peak spurious signal. the supply at its maximum limit. Aperture Jitter Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the ADC. Rev. C –5– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity (INL) Differential Nonlinearity (DNL, No Missing Codes) Zero Error Gain Error Temperature Drift Power Supply Rejection Aperture Jitter Aperture Delay Signal-to-Noise and Distortion Ratio (S/N+D, SINAD) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) TYPICAL PERFORMANCE CHARACTERISTICS INTRODUCTION ANALOG INPUT AND REFERENCE OVERVIEW ANALOG INPUT OPERATION REFERENCE OPERATION DRIVING THE ANALOG INPUTS SINGLE-ENDED MODE OF OPERATION DC COUPLING AND INTERFACE ISSUES Simple Op Amp Buffer Op Amp with DC Level Shifting AC COUPLING AND INTERFACE ISSUES Simple AC Interface Alternative AC Interface OP AMP SELECTION GUIDE DIFFERENTIAL MODE OF OPERATION REFERENCE CONFIGURATIONS USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 3 VREF Range Resistor Programmable Reference USING AN EXTERNAL REFERENCE Variable Input Span with VCM = 2.5 V Single-Ended Input with 0 to 2 ¥ VREF Range DIGITAL INPUTS AND OUTPUTS Digital Outputs Out-Of-Range (OTR) Digital Output Driver Considerations (DRVDD) Clock Input and Considerations Direct IF Down Conversion Using the AD9225 GROUNDING AND DECOUPLING Analog and Digital Grounding Analog and Digital Driver Supply Decoupling OUTLINE DIMENSIONS Ordering Guide REVISION HISTORY