Datasheet ADN4624 (Analog Devices) - 5

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ADN4624 SPECIFICATIONS Table 3. Parameter Symbol Min Typ Max1 Unit Test Conditions/Comments
MAXIMUM DATA RATE 2.5 Gbps 1 These specifications are guaranteed by design and characterization. 2 Duty cycle or pulse skew is the magnitude of the maximum difference between tPLH and tPHL for any Channel x of a device (where x = 1, 2, 3, or 4), that is, |tPLHx – tPHLx|. 3 Channel to channel or output skew is the difference between the largest and smallest values of tPLHx within a device or the difference between the largest and smallest values of tPHLx within a device, whichever of the two is greater. 4 Part to part output skew is the difference between the largest and smallest values of tPLHx across multiple devices or the difference between the largest and smallest values of tPHLx across multiple devices, whichever of the two is greater. 5 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter. VID = 400 mV p-p, VIC = 1.2 V, and tR / tF < 0.05 ns (20% to 80%). 6 This specification is measured over a population of ~3,000,000 edges. 7 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK(D)). 8 Using the following formula: tTJ(PP) = 14 × tRJ(RMS) + tDJ(PP). 9 With input phase jitter of 340 fs rms subtracted. 10With input phase jitter of 155 fs rms subtracted.
INSULATION AND SAFETY RELATED SPECIFICATIONS
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Table 4. RN-28-1 Wide Body with Finer Pitch [SOIC_W_FP] Package Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 5.7 kV rms 1 minute duration Minimum External Air Gap (Clearance) L (I01) 8.3 mm min Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L (I02) 8.3 mm min Measured from input terminals to output terminals, shortest distance path along body Minimum Clearance in the Plane of the Printed Circuit Board L (PCB) 8.1 mm min Measured from input terminals to output terminals, shortest distance (PCB Clearance) through air, line of sight, in the PCB mounting plane Minimum Internal Gap (Internal Clearance) 25.5 µm min Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >600 V Tested in accordance to IEC 60112 Material Group I Material Group per IEC 60664-1
PACKAGE CHARACTERISTICS Table 5. RN-28-1 Wide Body with Finer Pitch [SOIC_W_FP] Package Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1 RI-O 1013 Ω Voltage (input to output) (VI-O) = 500 VDC Capacitance (Input to Output)1 CI-O 2.2 pF Frequency = 1 MHz Input Capacitance2 CI 3.4 pF 1 The device is considered a 2-terminal device: Pin 1 through Pin 14 are shorted together, and Pin 15 through Pin 28 are shorted together. 2 Input capacitance is from any input data pin to ground.
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Document Outline Features Applications Functional Block Diagram General Description Specifications Receiver Input Threshold Test Voltages Timing Specifications Insulation and Safety Related Specifications Package Characteristics Regulatory Information DIN V VDE V 0884-11 (VDE V 0884-11) Insulation Characteristics (Pending) Recommended Operating Conditions Absolute Maximum Ratings Thermal Resistance Electrostatic Discharge (ESD) Ratings ESD Ratings for ADN4624 ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits and Switching Characteristics Theory of Operation Isolation and Refresh Truth Table Applications Information PCB Layout Application Examples Magnetic Field Immunity Insulation Lifetime Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example Outline Dimensions Ordering Guide Evaluation Boards