Datasheet ADN4624 (Analog Devices) - 4

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ADN4624 SPECIFICATIONS RECEIVER INPUT THRESHOLD TEST VOLTAGES Table 2. Test Voltages for Receiver Operation Applied Voltages DINx+ (V) DINx− (V) Input Voltage, Differential, VID (V) Input Voltage, Common-Mode, VIC (V) Driver Output, Differential VOD (mV)
1.25 1.15 0.1 1.2 >250 1.15 1.25 −0.1 +1.2 <−250 2.4 2.3 0.1 2.35 >250 2.3 2.4 −0.1 +2.35 <−250 0.1 0 0.1 0.05 >250 0 0.1 −0.1 +0.05 <−250 1.5 0.9 0.6 1.2 >250 0.9 1.5 −0.6 +1.2 <−250 2.4 1.8 0.6 2.1 >250 1.8 2.4 −0.6 +2.1 <−250 0.6 0 0.6 0.3 >250 0 0.6 −0.6 +0.3 <−250
TIMING SPECIFICATIONS
For all minimum and maximum specifications, VDD1 = VDD2 = 1.7 V to 1.9 V and TA = −40°C to +125°C, unless otherwise noted. For all typical specifications, VDD1 = VDD2 = 1.8 V and TA = 25°C. For all specifications, REFRESH1 = VDD1 and REFRESH2 = VDD2, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max1 Unit Test Conditions/Comments
PROPAGATION DELAY tPLH, tPHL 2.15 2.8 ns See Figure 29, from any DINx+ and DINx− to DOUTx+ and DOUTx− SKEW See Figure 29, across all DOUTx+ and DOUTx− Duty Cycle2 tSK(D) 2 16 ps Channel to Channel3 tSK(CH) 38 92 ps Part to Part4 tSK(PP) 150 300 ps JITTER5 See Figure 29, for any DOUTx+ and DOUTx− Random Jitter, RMS6 (1σ) tRJ(RMS) 0.82 1.44 ps rms 1.25 GHz clock input Deterministic Jitter, Peak to Peak6, 7 tDJ(PP) 28 54 ps 2.5 Gbps, 223 − 1 pseudorandom bit stream (PRBS) Total Jitter, Peak to Peak, at Bit Error Rate tTJ(PP) 40 70 ps 1.25 GHz/2.5 Gbps, 223 − 1 PRBS8 (BER) 1 × 10−12 With Crosstalk 50 ps 1.25 GHz/2.5 Gbps, 223 − 1 PRBS all channels8 With Crosstalk and Refresh 55 ps 1.25 GHz/2.5 Gbps, 223 − 1 PRBS all channels, REFRESH1 = GND1, REFRESH 8 2 = GND2 Additive Phase Jitter tADDJ 225 fs rms 100 Hz to 100 kHz, output frequency (fOUT) = 10 MHz9 270 fs rms 100 Hz to 100 kHz, fOUT = 10 MHz, REFRESH1 = GND1, REFRESH2 = GND 9 2 85 fs rms 12 kHz to 20 MHz, fOUT = 1.25 GHz10 200 fs rms 12 kHz to 20 MHz, fOUT = 1.25 GHz, REFRESH1 = GND1, REFRESH2 = GND 10 2 RISE AND FALL TIME tR, tF 180 ps See Figure 29, 1.25 GHz clock input, any DOUTx+ and DOUTx−, 20% to 80%, RL = 100 Ω, load capacitance (CL) = 5 pF
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Document Outline Features Applications Functional Block Diagram General Description Specifications Receiver Input Threshold Test Voltages Timing Specifications Insulation and Safety Related Specifications Package Characteristics Regulatory Information DIN V VDE V 0884-11 (VDE V 0884-11) Insulation Characteristics (Pending) Recommended Operating Conditions Absolute Maximum Ratings Thermal Resistance Electrostatic Discharge (ESD) Ratings ESD Ratings for ADN4624 ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits and Switching Characteristics Theory of Operation Isolation and Refresh Truth Table Applications Information PCB Layout Application Examples Magnetic Field Immunity Insulation Lifetime Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example Outline Dimensions Ordering Guide Evaluation Boards