Datasheet ADN4624 (Analog Devices)

link to page 20 link to page 20 link to page 1 link to page 20 link to page 20 Data Sheet
ADN4624
5.7 kV RMS, Quad-Channel LVDS 2.5 Gigabit Isolator
FEATURES FUNCTIONAL BLOCK DIAGRAM
► 5.7 kV rms LVDS isolators ► Complies with TIA/EIA-644-A LVDS signal levels ► Quad-channel configuration ► Any data rate up to 2.5 Gbps switching with low jitter ► 10 Gbps total bandwidth across four channels ► 2.15 ns typical propagation delay ► Typical jitter: 0.82 ps rms random, 40 ps total peak ► Lower power 1.8 V supplies ► ±8 kV IEC 61000-4-2 ESD protection across isolation barrier
Figure 1.
► High common-mode transient immunity: 100 kV/μs typical
GENERAL DESCRIPTION
► Safety and regulatory approvals (28-lead SOIC_W_FP package) ► UL (pending): 5700 V rms for 1 minute per UL 1577 The ADN46241 is a quad-channel, signal isolated, low voltage ► CSA Component Acceptance Notice 5A (pending) differential signaling (LVDS) buffer that operates at up to 2.5 Gbps ► VDE certificate of conformity (pending) with very low jitter. The device integrates Analog Devices, Inc., iCoupler® technology, enhanced for high speed operation to pro- ► DIN V VDE V 0884-11 (VDE V 0884-11):2017-01 vide drop-in galvanic isolation of LVDS signal chains. AC coupling ► VIORM = 849 VPEAK (working voltage) and/or level shifting to the LVDS receivers and from the LVDS ► Enable or disable refresh (low speed output correctness check) drivers allows isolation of other high speed signals such as current ► Operating temperature range: −40°C to +125°C mode logic (CML). ► 28-lead, wide body, fine pitch SOIC-FP package with 8.3 mm The ADN4624 includes a refresh mechanism to monitor the input creepage and clearance and output states and ensure they remain the same in the absence
APPLICATIONS
of data transitions (for example, at power-on). For lower power consumption and high speed operation with low ► Isolated video and imaging data jitter, the LVDS and isolator circuits rely on 1.8 V supplies. The ► Analog front-end isolation ADN4624 is fully specified over a wide industrial temperature range ► Data plane isolation and is available in a 28-lead, wide body, fine pitch SOIC-FP pack- ► Isolated high speed clock and data links age with 8.3 mm creepage and clearance (for 5.7 kV rms or 8 ► Multi-gigabit serialization/deserialization (SERDES) kVPEAK surge and impulse voltages and reinforced insulation at AC mains voltages). ► Board-to-board optical replacement (for example, short reach fiber) 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. 0 DOCUMENT FEEDBACK
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
TECHNICAL SUPPORT
registered trademarks are the property of their respective owners. Document Outline Features Applications Functional Block Diagram General Description Specifications Receiver Input Threshold Test Voltages Timing Specifications Insulation and Safety Related Specifications Package Characteristics Regulatory Information DIN V VDE V 0884-11 (VDE V 0884-11) Insulation Characteristics (Pending) Recommended Operating Conditions Absolute Maximum Ratings Thermal Resistance Electrostatic Discharge (ESD) Ratings ESD Ratings for ADN4624 ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits and Switching Characteristics Theory of Operation Isolation and Refresh Truth Table Applications Information PCB Layout Application Examples Magnetic Field Immunity Insulation Lifetime Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example Outline Dimensions Ordering Guide Evaluation Boards