Datasheet Summary SAM D21E, SAM D21G, SAM D21J (Microchip) - 9

FabricanteMicrochip
Descripción32-bit ARM-Based Microcontrollers
Páginas / Página59 / 9 — 32-bit ARM-Based Microcontrollers. Ordering Code. FLASH (bytes). SRAM …
Revisión02-01-2017
Formato / tamaño de archivoPDF / 3.3 Mb
Idioma del documentoInglés

32-bit ARM-Based Microcontrollers. Ordering Code. FLASH (bytes). SRAM (bytes). Package. Carrier Type. Datasheet Summary

32-bit ARM-Based Microcontrollers Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type Datasheet Summary

Línea de modelo para esta hoja de datos

ATSAMD21E15
ATSAMD21E15L
ATSAMD21E16
ATSAMD21E16L
ATSAMD21E17
ATSAMD21E18
ATSAMD21G15
ATSAMD21G16
ATSAMD21G16L
ATSAMD21G17
ATSAMD21G18
ATSAMD21J15
ATSAMD21J16
ATSAMD21J17
ATSAMD21J18

Versión de texto del documento

32-bit ARM-Based Microcontrollers Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type
ATSAMD21E16A-AU 64K 8K TQFP32 Tray ATSAMD21E16A-AUT Tape & Reel ATSAMD21E16A-AF Tray ATSAMD21E16A-AFT Tape & Reel ATSAMD21E16A-MU QFN32 Tray ATSAMD21E16A-MUT Tape & Reel ATSAMD21E16A-MF Tray ATSAMD21E16A-MFT Tape & Reel ATSAMD21E17A-AU 128K 16K TQFP32 Tray ATSAMD21E17A-AUT Tape & Reel ATSAMD21E17A-AF Tray ATSAMD21E17A-AFT Tape & Reel ATSAMD21E17A-MU QFN32 Tray ATSAMD21E17A-MUT Tape & Reel ATSAMD21E17A-MF Tray ATSAMD21E17A-MFT Tape & Reel ATSAMD21E18A-AU 256K 32K TQFP32 Tray ATSAMD21E18A-AUT Tape & Reel ATSAMD21E18A-AF Tray ATSAMD21E18A-AFT Tape & Reel ATSAMD21E18A-MU QFN32 Tray ATSAMD21E18A-MUT Tape & Reel ATSAMD21E18A-MF Tray ATSAMD21E18A-MFT Tape & Reel © 2017 Microchip Technology Inc.
Datasheet Summary
40001884A-page 9 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 3.1. SAM D21E 3.2. SAM D21G 3.3. SAM D21J 3.4. Device Identification 4. Block Diagram 5. Pinout 5.1. SAM D21J 5.1.1. QFN64 / TQFP64 5.1.2. UFBGA64 5.2. SAM D21G 5.2.1. QFN48 / TQFP48 5.2.2. WLCSP45 5.3. SAM D21E 5.3.1. QFN32 / TQFP32 5.3.2. WLCSP35 6. Product Mapping 7. Processor And Architecture 7.1. Cortex M0+ Processor 7.1.1. Cortex M0+ Configuration 7.1.2. Cortex-M0+ Peripherals 7.1.3. Cortex-M0+ Address Map 7.1.4. I/O Interface 7.1.4.1. Overview 7.1.4.2. Description 7.2. Nested Vector Interrupt Controller 7.2.1. Overview 7.2.2. Interrupt Line Mapping 7.3. Micro Trace Buffer 7.3.1. Features 7.3.2. Overview 7.4. High-Speed Bus System 7.4.1. Features 7.4.2. Configuration 7.4.3. SRAM Quality of Service 7.5. AHB-APB Bridge 7.6. PAC - Peripheral Access Controller 7.6.1. Overview 7.6.2. Register Description 7.6.2.1. PAC0 Register Description 7.6.2.1.1. Write Protect Clear 7.6.2.1.2. Write Protect Set 7.6.2.2. PAC1 Register Description 7.6.2.2.1. Write Protect Clear 7.6.2.2.2. Write Protect Set 7.6.2.3. PAC2 Register Description 7.6.2.3.1. Write Protect Clear 7.6.2.3.2. Write Protect Set 8. Packaging Information 8.1. Thermal Considerations 8.1.1. Thermal Resistance Data 8.1.2. Junction Temperature 8.2. Package Drawings 8.2.1. 64 pin TQFP 8.2.2. 64 pin QFN 8.2.3. 64-ball UFBGA 8.2.4. 48 pin TQFP 8.2.5. 48 pin QFN 8.2.6. 45-ball WLCSP 8.2.7. 32 pin TQFP 8.2.8. 32 pin QFN 8.2.9. 35 ball WLCSP (Device Variant B) 8.2.10. 35 ball WLCSP (Device Variant C) 8.3. Soldering Profile The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service