Datasheet AD7765 (Analog Devices) - 6

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AD7765 Parameter Test Conditions/Comments Specification Unit
Normal Power Mode AIDD1 (Modulator) 19 mA typ AIDD2 (General)5 MCLK = 40 MHz 13 mA typ AIDD3 (Differential Amplifier) AVDD3 = 5 V 10 mA typ AIDD4 (Reference Buffer) AVDD4 = 5 V 9 mA typ DI 5 DD MCLK = 40 MHz 37 mA typ Low Power Mode AIDD1 (Modulator) 10 mA typ AIDD2 (General)5 MCLK = 40 MHz 7 mA typ AIDD3 (Differential Amplifier) AVDD3 = 5 V 5.5 mA typ AIDD4 (Reference Buffer) AVDD4 = 5 V 5 mA typ DI 5 DD MCLK = 40 MHz 20 mA typ POWER DISSIPATION Normal Power Mode MCLK = 40 MHz, decimate 128× 300 mW typ 371 mW max Low Power Mode MCLK = 40 MHz, decimate 128× 160 mW typ 215 mW max Power-Down Mode6 PWRDWN held logic low 1 mW typ 1 See Terminology section. 2 SNR specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 3 Output data rate (ODR) = [(MCLK/2)]/decimation rate. That is, the maximum ODR for AD7765 = [(40 MHz/2)/128] = 156.25 kHz. 4 Tested with a 400 µA load current. 5 Tested at MCLK = 40 MHz. This current scales linearly with the MCLK frequency applied. 6 Tested at 125°C. Rev. A | Page 5 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Σ-Δ Modulation and Digital Filtering AD7765 Antialias Protection AD7765 Input Structure On-Chip Differential Amplifier Modulator Input Structure Driving the Modulator Inputs Directly AD7765 Interface Reading Data Reading Status and Other Registers Writing to the AD7765 AD7765 Functionality Synchronization Overrange Alerts Power Modes Low Power Mode RESET/PWRDWN Mode Decimation Rate Pin Daisy Chaining Reading Data in Daisy-Chain Mode Writing Data in Daisy-Chain Mode Clocking the AD7765 MCLK Jitter Requirements Example 1 Example 2 Decoupling and Layout Information Supply Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Using the AD7765 Bias Resistor Selection AD7765 Registers Control Register Status Register Gain Register—Address 0x0004 Non-Bit-Mapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-Bit-Mapped, Default Value 0xCCCC Outline Dimensions Ordering Guide