Datasheet AD7765 (Analog Devices) - 7

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AD7765 TIMING SPECIFICATIONS
AVDD1 = DVDD = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF+ = 4.096 V, TA = 25°C, CLOAD = 25 pF.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
fMCLK 500 kHz min Applied master clock frequency 40 MHz max fICLK 250 kHz min Internal modulator clock derived from MCLK 20 MHz max t1 1 × tICLK typ SCO high period t2 1 × tICLK typ SCO low period t3 1 ns typ SCO rising edge to FSO falling edge t4 2 ns typ Data access time, FSO falling edge to data active t5 8 ns max MSB data access time, SDO active to SDO valid t6 40 ns min Data hold time (SDO valid to SCO rising edge) t7 9.5 ns max Data access time (SCO rising edge to SDO valid) t8 2 ns typ SCO rising edge to FSO rising edge t9 32 × tSCO max FSO low period t10 12 ns min Setup time from FSI falling edge to SCO falling edge t11 1 × tSCO min FSI low period t 1 12 32 × tSCO max FSI low period t13 12 ns min SDI setup time for the first data bit t14 12 ns min SDI setup time t15 0 ns max SDI hold time tR MIN 1 × tMCLK min Minimum time for a valid RESET pulse tR HOLD 5 ns min Minimum time between the MCLK rising edge and RESET rising edge tR SETUP 5 ns min Minimum time between the RESET rising edge and MCLK rising edge tS MIN 4 × tMCLK min Minimum time for a valid SYNC pulse tS HOLD 5 ns min Minimum time between the MCLK falling edge and SYNC rising edge tS SETUP 5 ns min Minimum time between the SYNC rising edge and MCLK falling edge 1 This is the maximum time FSI can be held low when writing to an individual device (a device that is not daisy-chained). Rev. A | Page 6 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Σ-Δ Modulation and Digital Filtering AD7765 Antialias Protection AD7765 Input Structure On-Chip Differential Amplifier Modulator Input Structure Driving the Modulator Inputs Directly AD7765 Interface Reading Data Reading Status and Other Registers Writing to the AD7765 AD7765 Functionality Synchronization Overrange Alerts Power Modes Low Power Mode RESET/PWRDWN Mode Decimation Rate Pin Daisy Chaining Reading Data in Daisy-Chain Mode Writing Data in Daisy-Chain Mode Clocking the AD7765 MCLK Jitter Requirements Example 1 Example 2 Decoupling and Layout Information Supply Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Using the AD7765 Bias Resistor Selection AD7765 Registers Control Register Status Register Gain Register—Address 0x0004 Non-Bit-Mapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-Bit-Mapped, Default Value 0xCCCC Outline Dimensions Ordering Guide