Datasheet MCP6491, MCP6492, MCP6494 (Microchip) - 13

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MCP6491/2/4 3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE MCP6491 MCP6492 MCP6494 Symbol Description
SC70, SOT-23 SOIC, MSOP 2x3 TDFN SOIC, TSSOP 1 1 1 1 VOUT, VOUTA Analog Output (op amp A) 4 2 2 2 VIN–, VINA– Inverting Input (op amp A) 3 3 3 3 VIN+, VINA+ Non-inverting Input (op amp A) 5 8 8 4 VDD Positive Power Supply — 5 5 5 VINB+ Non-Inverting Input (op amp B) — 6 6 6 VINB– Inverting Input (op amp B) — 7 7 7 VOUTB Analog Output (op amp B) — — — 8 VOUTC Analog Output (op amp C) — — — 9 VINC– Inverting Input (op amp C) — — — 10 VINC+ Non-Inverting Input (op amp C) 2 4 4 11 VSS Negative Power Supply — — — 12 VIND+ Non-Inverting Input (op amp D) — — — 13 VIND– Inverting Input (op amp D) — — — 14 VOUTD Analog Output (op amp D) — — 9 — EP Exposed Thermal Pad (EP); must be connected to VSS.
3.1 Analog Outputs 3.4 Exposed Thermal Pad (EP)
The output pins are low-impedance voltage sources. There is an internal electrical connection between the Exposed Thermal Pad (EP) and the VSS pin; they must
3.2 Analog Inputs
be connected to the same potential on the Printed Circuit Board (PCB). The non-inverting and inverting inputs are This pad can be connected to a PCB ground plane to high-impedance CMOS inputs with low bias currents. provide a larger heat sink. This improves the package thermal resistance (
3.3 Power Supply Pins
JA). The positive power supply (VDD) is 2.4V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in single-supply opera- tion. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors.  2012-2013 Microchip Technology Inc. DS20002321C-page 13 Document Outline Package Types Typical Application 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings 1.2 Specifications 1.3 Test Circuits 2.0 Typical Performance Curves Figure 2-1: Input Offset Voltage Figure 2-2: Input Offset Voltage Drift Figure 2-3: Input Offset Voltage vs. Common Mode Input Voltage Figure 2-4: Input Offset Voltage vs. Common Mode Input Voltage Figure 2-5: Input Offset Voltage vs. Output Voltage Figure 2-6: Input Offset Voltage vs. Power Supply Voltage FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-11: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-12: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-13: Quiescent Current vs. Ambient Temperature. FIGURE 2-14: Quiescent Current vs. Common Mode Input Voltage. FIGURE 2-15: Quiescent Current vs. Common Mode Input Voltage. FIGURE 2-16: Quiescent Current vs. Power Supply Voltage. FIGURE 2-17: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-18: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-22: Output Voltage Swing vs. Frequency. FIGURE 2-23: Output Voltage Headroom vs. Output Current. FIGURE 2-24: Output Voltage Headroom vs. Output Current. FIGURE 2-25: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-26: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-27: Slew Rate vs. Ambient Temperature. FIGURE 2-28: Small Signal Non-Inverting Pulse Response. FIGURE 2-29: Small Signal Inverting Pulse Response. FIGURE 2-30: Large Signal Non-Inverting Pulse Response. FIGURE 2-31: Large Signal Inverting Pulse Response. FIGURE 2-32: The MCP6491/2/4 Shows No Phase Reversal. FIGURE 2-33: Closed Loop Output Impedance vs. Frequency. FIGURE 2-34: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-35: Channel-to-Channel Separation vs. Frequency (MCP6492/4 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. Figure 4-3: Protecting the Analog Inputs 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps Figure 4-6: Unused Op Amps. Figure 4-7: Example Guard Ring Layout for Inverting Gain 4.6 PCB Surface Leakage 4.7 Application Circuits FIGURE 4-8: Photovoltaic Mode Detector. FIGURE 4-9: Photoconductive Mode Detector. FIGURE 4-10: Second-Order, Low-Pass Butterworth Filter with Sallen-Key Topology. FIGURE 4-11: Second-Order, Low-Pass Butterworth Filter with Multiple-Feedback Topology. FIGURE 4-12: pH Electrode Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service