Datasheet AD9680 (Analog Devices) - 6

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AD9680 Data Sheet AD9680-500 AD9680-820 AD9680-1000 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit
POWER CONSUMPTION Total Power Dissipation Full 2.2 2.9 3.3 W (Including Output Drivers)2, 4 Total Power Dissipation (L = 2 25°C 2.1 N/A3 N/A3 Mode) Power-Down Dissipation Full 700 820 835 mW Standby5 Full 1.2 1.3 1.4 W 1 All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used. 2 Default mode. No DDCs used. L = 4, M = 2, F = 1. 3 N/A means not applicable. At the maximum sample rate, it is not applicable to use L = 2 mode on the JESD204B output interface because this exceeds the maximum lane rate of 12.5 Gbps. L = 2 mode is supported when the equation ((M × N΄ × (10/8) × fOUT)/L) results in a line rate that is ≤12.5 Gbps. fOUT is the output sample rate and is denoted by fS/DCM, where DCM is the decimation ratio. 4 Default mode. No DDCs used. 5 Can be controlled by the SPI.
AC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 2. AD9680-500 AD9680-820 AD9680-1000 Parameter1 Temperature Min Typ Max Min Typ Max Min Typ Max Unit
ANALOG INPUT FULL SCALE Full 2.06 1.7 1.7 V p-p NOISE DENSITY2 Full −153 −153 −154 dBFS/Hz SIGNAL-TO-NOISE RATIO (SNR)3 fIN = 10 MHz 25°C 69.2 67.2 67.2 dBFS fIN = 170 MHz Full 67.8 69.0 65.6 67.0 65.1 66.6 dBFS fIN = 340 MHz 25°C 68.6 66.5 65.3 dBFS fIN = 450 MHz 25°C 68.0 65.1 64.0 dBFS fIN = 765 MHz 25°C 64.4 64.0 61.5 dBFS fIN = 985 MHz 25°C 63.8 63.4 60.5 dBFS fIN = 1950 MHz 25°C 60.5 59.7 57.0 dBFS SNR AND DISTORTION RATIO (SINAD)3 fIN = 10 MHz 25°C 69.0 67.1 67.1 dBFS fIN = 170 MHz Full 67.6 68.8 65.2 66.8 65.0 66.4 dBFS fIN = 340 MHz 25°C 68.4 66.3 65.2 dBFS fIN = 450 MHz 25°C 67.9 64.7 63.8 dBFS fIN = 765 MHz 25°C 64.2 63.5 62.1 dBFS fIN = 985 MHz 25°C 63.6 62.7 61.1 dBFS fIN = 1950 MHz 25°C 60.3 58.7 56.0 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 11.2 10.9 10.8 Bits fIN = 170 MHz Full 10.9 11.1 10.5 10.8 10.5 10.7 Bits fIN = 340 MHz 25°C 11.1 10.7 10.5 Bits fIN = 450 MHz 25°C 11.0 10.5 10.3 Bits fIN = 765 MHz 25°C 10.4 10.3 10.0 Bits fIN = 985 MHz 25°C 10.3 10.1 9.8 Bits fIN = 1950 MHz 25°C 9.7 9.5 9.0 Bits Rev. B | Page 6 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9680-1000 AD9680-820 AD9680-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B TX CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE