Datasheet AD9680 (Analog Devices) - 10

AD9680 Data Sheet Timing Diagrams APERTURE DELAY SAMPLE N ANALOG INPUT N – 54 N + 1 SIGNAL N – 55 N – 53 N – 52 N – 51 N – 1 CLK– CLK+ CLK– CLK+ SERDOUT0– A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 MSB SERDOUT0+ SERDOUT1– A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 LSB SERDOUT1+ SERDOUT2– A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 MSB SERDOUT2+ SERDOUT3– A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 LSB SERDOUT3+ SAMPLE N – 55 SAMPLE N – 54 SAMPLE N – 53
002
ENCODED INTO 1 ENCODED INTO 1 ENCODED INTO 1
52-
8-BIT/10-BIT SYMBOL 8-BIT/10-BIT SYMBOL 8-BIT/10-BIT SYMBOL
117 Figure 2. Data Output Timing (Full Bandwidth Mode; L = 4; M = 2; F = 1)
CLK– CLK+ tSU_SR tH_SR SYSREF–
03 0 2-
SYSREF+
175 1 Figure 3. SYSREF± Setup and Hold Timing
tDS tHIGH tCLK tACCESS tH tS tDH tLOW CSB SCLK DON’T CARE DON’T CARE
004
SDIO DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE
1752- 1 Figure 4. Serial Port Interface Timing Diagram Rev. B | Page 10 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9680-1000 AD9680-820 AD9680-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B TX CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE