Datasheet AD9680 (Analog Devices)

14-Bit, 1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9680 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD JESD204B (Subclass 1) coded serial digital outputs (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V) 1.65 W total power per channel at 1 GSPS (default settings) SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz BUFFER VIN+A ADC SNR at 1 GSPS = 65.3 dBFS at 340 MHz (A 14 CORE IN = −1.0 dBFS), VIN–A ER DDC IZ 60.5 dBFS at 1 GHz (A L IN = −1.0 dBFS) FD_A IA T TS T 4B C U SERDOUT0± ENOB = 10.8 bits at 10 MHz ER 4 S E SIGNAL 20 S TP SERDOUT1± MONITOR U SERDOUT2± FA DNL = ±0.5 LSB DET JESD O SERDOUT3± FD_B Tx SPEED INL = ±2.5 LSB 14 H DDC VIN+B IG ADC H Noise density = −154 dBFS/Hz at 1 GSPS VIN–B CORE 1.25 V, 2.5 V, and 3.3 V dc supply operation BUFFER CONTROL No missing codes REGISTERS V_1P0 FAST Internal ADC voltage reference DETECT SIGNAL Flexible input range SYNCINB± JESD204B MONITOR CLOCK SUBCLASS 1 AD9680-1000 and AD9680-820: 1.46 V p-p to 1.94 V p-p GENERATION CONTROL SYSREF± (1.70 V p-p nominal) CLK+ AD9680-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) CLK– ÷2 SPI CONTROL PDWN/ ÷4 STBY Programmable termination impedance AD9680 ÷8
01
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
-0
AGND DRGND DGND SDIO SCLK CSB
752
2 GHz usable analog input full power bandwidth
11 Figure 1.
95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation PRODUCT HIGHLIGHTS 2 integrated wideband digital processors per channel
1. Wide full power bandwidth supports IF sampling of signals
12-bit NCO, up to 4 cascaded half-band filters
up to 2 GHz.
Differential clock input
2. Buffered inputs with programmable input termination eases
Integer clock divide by 1, 2, 4, or 8
filter design and implementation.
Flexible JESD204B lane configurations
3. Four integrated wideband decimation filters and numerically
Small signal dither
controlled oscillator (NCO) blocks supporting multiband
APPLICATIONS
receivers. 4. Flexible serial port interface (SPI) controls various product
Communications
features and functions to meet specific system requirements.
Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
5. Programmable fast overrange detection.
General-purpose software radios
6. 9 mm × 9 mm, 64-lead LFCSP.
Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9680-1000 AD9680-820 AD9680-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B TX CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE