Datasheet AD9680 (Analog Devices) - 4

AD9680 Data Sheet GENERAL DESCRIPTION
The AD9680 is a dual, 14-bit, 1 GSPS/500 MSPS analog-to-digital function in the communications receiver. The programmable converter (ADC). The device has an on-chip buffer and sample- threshold detector allows monitoring of the incoming signal and-hold circuit designed for low power, small size, and ease of power using the fast detect output bits of the ADC. If the input use. This device is designed for sampling wide bandwidth analog signal level exceeds the programmable threshold, the fast detect signals of up to 2 GHz. The AD9680 is optimized for wide input indicator goes high. Because this threshold indicator has low bandwidth, high sampling rate, excellent linearity, and low power latency, the user can quickly turn down the system gain to avoid in a small package. an overrange condition at the ADC input. The dual ADC cores feature a multistage, differential pipelined Users can configure the Subclass 1 JESD204B-based high speed architecture with integrated output error correction logic. Each serialized output in a variety of one-, two-, or four-lane ADC features wide bandwidth inputs supporting a variety of configurations, depending on the DDC configuration and the user-selectable input ranges. An integrated voltage reference acceptable lane rate of the receiving logic device. Multiple device eases design considerations. synchronization is supported through the SYSREF± and The analog input and clock signals are differential inputs. Each SYNCINB± input pins. ADC data output is internally connected to two digital down- The AD9680 has flexible power-down options that allow converters (DDCs). Each DDC consists of four cascaded signal significant power savings when desired. All of these features can processing stages: a 12-bit frequency translator (NCO), and four be programmed using a 1.8 V to 3.3 V capable 3-wire SPI. half-band decimation filters. The DDCs are bypassed by default. The AD9680 is available in a Pb-free, 64-lead LFCSP and is In addition to the DDC blocks, the AD9680 has several specified over the −40°C to +85°C industrial temperature range. functions that simplify the automatic gain control (AGC) This product is protected by a U.S. patent. Rev. B | Page 4 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9680-1000 AD9680-820 AD9680-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B TX CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE