Datasheet AD8330 (Analog Devices) - 3

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Data Sheet AD8330 SPECIFICATIONS
VS = 5 V, TA = 25°C, CL = 12 pF on OPHI and OPLO, RL = ∞, VDBS = 0.75 V, VMODE = high, VMAG = Pin VMAG open circuit (0.5 V), VOFST = 0 V, differential operation, unless otherwise noted.
Table 1. Parameter Conditions Min Typ Max Unit
INPUT INTERFACE Pin INHI, Pin INLO Full-Scale Input VDBS = 0 V, differential drive ±1.4 ±2 V VDBS = 1.5 V ±4.5 ±6.3 mV Input Resistance Pin-to-pin 800 1 k 1.2 k Ω Input Capacitance Either pin to COMM 4 pF Voltage Noise Spectral Density f = 1 MHz, VDBS = 1.5 V; inputs ac-shorted 5 nV/√Hz Common-Mode Voltage Level 2.75 3.0 3.25 V Input Offset Pin OFST connected to Pin COMM 1 mV rms Drift 2 μV/°C Permissible CM Range1 0 VS V Common-Mode AC Rejection f = 1 MHz, 0.1 V rms −60 dB f = 50 MHz −55 dB OUTPUT INTERFACE Pin OPHI, Pin OPLO Small Signal –3 dB Bandwidth 0 V < VDBS < 1.5 V 150 MHz Peak Slew Rate VDBS = 0 V 1500 V/μs Peak-to-Peak Output Swing ±1.8 ±2 ±2.2 V VMAG ≥ 2 V (peaks are supply limited) ±4 ±4.5 V Common-Mode Voltage Pin CNTR O/C 2.4 2.5 2.6 V Offset Voltage Offset Correction Enabled 1 ±5 mV Offset Correction Disabled Pin OFST connected to ground 8 ±40 mV Voltage Noise Spectral Density f = 1 MHz, VDBS = 0 V 62 nV/√Hz Differential Output Impedance Pin-to-pin 120 150 180 Ω HD22 VOUT = 1 V p-p, f = 10 MHz, RL = 1 kΩ −62 dBc HD32 VOUT = 1 V p-p, f = 10 MHz, RL = 1 kΩ −53 dBc OUTPUT OFFSET CONTROL Pin OFST AC-Coupled Offset CHPF on Pin OFST (0 V < VDBS < 1.5 V) 10 mV rms High-Pass Corner Frequency CHPF = 3.3 nF, from OFST to CNTR (scales as 1/CHPF) 100 kHz COMMON-MODE CONTROL Pin CNTR Usable Voltage Range 0.5 4.5 V Input Resistance From Pin CNTR to VS/2 4 kΩ DECIBEL GAIN CONTROL VDBS, CMGN, and MODE pins Normal Voltage Range CMGN connected to COMM 0 to 1.5 V Elevated Range CMGN O/C (VCMGN rises to 0.2 V) 0.2 to 1.7 V Gain Scaling Mode high or low 27 30 33 mV/dB Gain Linearity Error 0.3 V ≤ VDBS ≤ 1.2 V −0.35 ±0.1 +0.35 dB Absolute Gain Error VDBS = 0 V −2 ±0.5 +2 dB Bias Current Flows out of Pin VDBS 100 nA Incremental Resistance 100 MΩ Gain Settling Time to 0.5 dB Error VDBS stepped from 0.05 V to 1.45 V or 1.45 V to 0.05 V 250 ns Mode Up/Down Pin MODE Mode Up Logic Level Gain increases with VDBS, MODE = O/C 1.5 V Mode Down Logic Level Gain decreases with VDBS 0.5 V Rev. G | Page 3 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Circuit Description Overall Structure Normal Operating Conditions Linear-in-dB Gain Control (VDBS) Inversion of the Gain Slope Gain Magnitude Control (VMAG) Two Classes of Variable Gain Amplifiers Amplitude/Phase Response Noise, Input Capacity, and Dynamic Range Dynamic Range Input Common-Mode Range and Rejection Ratio Output Noise and Peak Swing Offset Compensation Effects of Loading on Gain and AC Response Gain Errors Due to On-Chip Resistor Tolerances Output (Input) Common-Mode Control Using the AD8330 Gain and Swing Adjustments When Loaded Input Coupling DC-Coupled Signal Path Using Single-Sided Sources and Loads Pulse Operation Preserving Absolute Gain Calculation of Noise Figure Noise as a Function of VDBS Distortion Considerations P1dB and V1dB Applications Information ADC Driving Simple AGC Amplifier Wide Range True RMS Voltmeter Evaluation Board General Description Basic Operation Options Measurement Setup AD8330-EVALZ Board Design Outline Dimensions Ordering Guide