Datasheet AD8330 (Analog Devices)

Low Cost, DC to 150 MHz Variable Gain Amplifier Data Sheet AD8330 FEATURES FUNCTIONAL BLOCK DIAGRAM ENBL OFST CNTR Fully differential signal path, also used with single-sided signals CM AND Inputs from 0.3 mV to 1 V rms, rail-to-rail outputs BIAS AND V OFFSET REF Differential R CONTROL IN = 1 kΩ; ROUT (each output) 75 Ω Automatic offset compensation (optional) INHI OPHI Linear-in-dB and linear-in-magnitude gain modes VGA CORE OUTPUT STAGES 0 dB to 50 dB, for 0 V < VDBS < 1.5 V (30 mV/dB) INLO OPLO Inverted gain mode: 50 dB to 0 dB at −30 mV/dB ×0.03 to ×10 nominal gain for 15 mV < V OUTPUT MAG < 5 V MODE GAIN INTERFACE CMOP CONTROL Constant bandwidth: 150 MHz at all gains Low noise: 5 nV/√Hz typical at maximum gain
101
Low distortion: ≤−62 dBc typical VDBS CMGN COMM VMAG
03217-
Low power: 20 mA typical at V
Figure 1.
S of 2.7 V to 6 V Available in a space-saving, 3 mm × 3 mm LFCSP package APPLICATIONS Pre-ADC signal conditioning 75 Ω cable driving adjust AGC amplifiers GENERAL DESCRIPTION
The AD8330 is a wideband variable gain amplifier for applications Using VMAG, the basic 0 dB to 50 dB range can be reposi- requiring a ful y differential signal path, low noise, wel -defined tioned to any value from 20 dB higher (that is, 20 dB to 70 dB) gain, and moderately low distortion, from dc to 150 MHz. The to at least 30 dB lower (that is, –30 dB to +20 dB) to suit the input pins can also be driven from a single-ended source. The application, thereby providing an unprecedented gain range of peak differential input is ±2 V, al owing sine wave operation at over 100 dB. A unique aspect of the AD8330 is that its bandwidth 1 V rms with generous headroom. The output pins can drive and pulse response are essential y constant for al gains, over both single-sided loads essential y rail-to-rail. The differential output the basic 50 dB linear-in-dB range, but also when using the resistance is 150 Ω. The output swing is a linear function of the linear-in-magnitude function. The exceptional stability of the voltage applied to the VMAG pin that internal y defaults to 0.5 V, HF response over the gain range is of particular value in those providing a peak output of ±2 V. This can be raised to 10 V p-p, VGA applications where it is essential to maintain accurate gain limited by the supply voltage. law-conformance at high frequencies. The basic gain function is linear-in-dB, control ed by the voltage An external capacitor at Pin OFST sets the high-pass corner of applied to Pin VDBS. The gain ranges from 0 dB to 50 dB for an offset reduction loop, whose frequency can be as low as 5 Hz. control voltages between 0 V and 1.5 V—a slope of 30 mV/dB. When this pin is grounded, the signal path becomes dc-coupled. The gain linearity is typical y within ±0.1 dB. By changing the When used to drive an ADC, an external common-mode control logic level on Pin MODE, the gain decreases over the same range, voltage at Pin CNTR can be driven to within 0.5 V of either ground with an opposite slope. A second gain control port is provided at or VS to accommodate a wide variety of requirements. By default, the VMAG pin and al ows the user to vary the numeric gain from the two outputs are positioned at the midpoint of the supply, VS/2. a factor of 0.03 to 10. Al the parameters of the AD8330 have low Other features, such as two levels of power-down (ful y off and a sensitivities to temperature and supply voltages. hibernate mode), further extend the practical value of this excep- tional y versatile VGA. The AD8330 is available in 16-lead LFCSP and 16-lead QSOP packages and is specified for operation from −40°C to +85°C.
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Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Circuit Description Overall Structure Normal Operating Conditions Linear-in-dB Gain Control (VDBS) Inversion of the Gain Slope Gain Magnitude Control (VMAG) Two Classes of Variable Gain Amplifiers Amplitude/Phase Response Noise, Input Capacity, and Dynamic Range Dynamic Range Input Common-Mode Range and Rejection Ratio Output Noise and Peak Swing Offset Compensation Effects of Loading on Gain and AC Response Gain Errors Due to On-Chip Resistor Tolerances Output (Input) Common-Mode Control Using the AD8330 Gain and Swing Adjustments When Loaded Input Coupling DC-Coupled Signal Path Using Single-Sided Sources and Loads Pulse Operation Preserving Absolute Gain Calculation of Noise Figure Noise as a Function of VDBS Distortion Considerations P1dB and V1dB Applications Information ADC Driving Simple AGC Amplifier Wide Range True RMS Voltmeter Evaluation Board General Description Basic Operation Options Measurement Setup AD8330-EVALZ Board Design Outline Dimensions Ordering Guide