Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices) - 10

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ADSP-BF700/701/702/703/704/705/706/707 ADDITIONAL PROCESSOR PERIPHERALS
After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in its The processor contains a rich set of peripherals connected to the timer control register that is set only upon a watchdog-gener- core through several high-bandwidth buses, providing flexibility ated reset. in system configuration as well as excellent overall system per- formance (see the block diagram on Page 1). The processor
Serial Ports (SPORTs)
contains high-speed serial and parallel ports, an interrupt con- Two synchronous serial ports (comprised of four half-SPORTs) troller for flexible management of interrupts from the on-chip provide an inexpensive interface to a wide variety of digital and peripherals or external sources, and power management control mixed-signal peripheral devices such as Analog Devices’ audio functions to tailor the performance and power characteristics of codecs, ADCs, and DACs. Each half-SPORT is made up of two the processor and system to many application scenarios. data lines, a clock, and frame sync. The data lines can be pro- The following sections describe additional peripherals that were grammed to either transmit or receive and each data line has a not previously described. dedicated DMA channel.
Timers
Serial port data can be automatically transferred to and from on-chip memory/external memory through dedicated DMA The processor includes several timers which are described in the channels. Each of the serial ports can work in conjunction with following sections. another serial port to provide TDM support. In this
General-Purpose Timers
configuration, one SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame There is one GP timer unit, and it provides eight general-pur- sync and clock are shared. pose programmable timers. Each timer has an external pin that can be configured either as a pulse width modulator (PWM) or Serial ports operate in six modes: timer output, as an input to clock the timer, or as a mechanism • Standard DSP serial mode for measuring pulse widths and periods of external events. • Multichanne l (TDM) mode These timers can be synchronized to an external clock input on the TIMER_TMRx pins, an external TIMER_CLK input pin, or • I2S mode to the internal SCLK0. • Packed I2S mode These timer units can be used in conjunction with the UARTs • Left-justified mode and the CAN controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function • Right-justified mode for the respective serial channels.
General-Purpose Counters
The GP timers can generate interrupts to the processor core, A 32-bit counter is provided that can operate in general-pur- providing periodic events for synchronization to either the sys- pose up/down count modes and can sense 2-bit quadrature or tem clock or to external signals. Timer events can also trigger binary codes as typically emitted by industrial drives or manual other peripherals through the TRU (for instance, to signal a thumbwheels. Count direction is either controlled by a level- fault). Each timer may also be started and/or stopped by any sensitive input pin or by two edge detectors. TRU master without core intervention. A third counter input can provide flexible zero marker support
Core Timer
and can alternatively be used to input the push-button signal of The processor core also has its own dedicated timer. This extra thumbwheel devices. All three pins have a programmable timer is clocked by the internal processor clock and is typically debouncing circuit. used as a system tick clock for generating periodic operating Internal signals forwarded to a GP timer enable this timer to system interrupts. measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by inter-
Watchdog Timer
rupts when programmed count values are exceeded. The core includes a 32-bit timer, which may be used to imple- ment a software watchdog function. A software watchdog can
Parallel Peripheral Interface (PPI)
improve system availability by forcing the processor to a known The processor provides a parallel peripheral interface (PPI) that state, through generation of a hardware reset, nonmaskable supports data widths up to 18 bits. The PPI supports direct con- interrupt (NMI), or general-purpose interrupt, if the timer nection to TFT LCD panels, parallel analog-to-digital and expires before being reset by software. The programmer initial- digital-to-analog converters, video encoders and decoders, izes the count value of the timer, enables the appropriate image sensor modules, and other general-purpose peripherals. interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts down to zero from the pro- grammed value. This protects the system from remaining in an unknown state where software that would normally reset the timer has stopped running due to an external noise condition or software error. Rev. D | Page 10 of 114 | February 2019 Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide