Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices) - 9

ADSP-BF700/701/702/703/704/705/706/707 PROCESSOR SAFETY FEATURES
Synonymously, the system memory protection unit (SMPU) provides memory protection against read and/or write transac- The ADSP-BF70x processor has been designed for functional tions to defined regions of memory. There are two SMPU units safety applications. While the level of safety is mainly domi- in the ADSP-BF70x processors. One is for the L2 memory and nated by the system concept, the following primitives are the other is for the external DDR memory. provided by the devices to build a robust safety concept. The SMPU is also part of the security infrastructure. It allows
Multi-Parity-Bit-Protected L1 Memories
the user to not only protect against arbitrary read and/or write In the processor’s L1 memory space, whether SRAM or cache, transactions, but it also allows regions of memory to be defined each word is protected by multiple parity bits to detect the single as secure and prevent non-secure masters from accessing those event upsets that occur in all RAMs. This applies both to L1 memory regions. instruction and data memory spaces.
Watchpoint Protection ECC-Protected L2 Memories
The primary purpose of watchpoints and hardware breakpoints Error correcting codes (ECC) are used to correct single event is to serve emulator needs. When enabled, they signal an emula- upsets. The L2 memory is protected with a single error correct- tor event whenever user-defined system resources are accessed double error detect (SEC-DED) code. By default ECC is or the core executes from user-defined addresses. Watchpoint enabled, but it can be disabled on a per-bank basis. Single-bit events can be configured such that they signal the events to the errors are transparently corrected. fault management unit of the SEC. Dual-bit errors can issue a system event or fault if enabled. ECC
Watchdog
protection is fully transparent to the user, even if L2 memory is The on-chip software watchdog timer can supervise the read or written by 8-bit or 16-bit entities. Blackfin+ core.
CRC-Protected Memories Bandwidth Monitor
While parity bit and ECC protection mainly protect against ran- Memory-to-memory DMA channels are equipped with a band- dom soft errors in L1 and L2 memory cells, the CRC engines can width monitor mechanism. They can signal a system event or be used to protect against systematic errors (pointer errors) and fault when transactions tend to starve because system buses are static content (instruction code) of L1, L2, and even L3 memo- fully loaded with higher-priority traffic. ries (DDR2, LPDDR). The processor features two CRC engines which are embedded in the memory-to-memory DMA
Signal Watchdogs
controllers. CRC checksums can be calculated or compared on The eight general-purpose timers feature modes to monitor off- the fly during memory transfers, or one or multiple memory chip signals. The watchdog period mode monitors whether regions can be continuously scrubbed by a single DMA work external signals toggle with a period within an expected range. unit as per DMA descriptor chain instructions. The CRC engine The watchdog width mode monitors whether the pulse widths also protects data loaded during the boot process. of external signals are within an expected range. Both modes
Memory Protection
help to detect undesired toggling (or lack thereof) of  system-level signals. The Blackfin+ core features a memory protection concept, which grants data and/or instruction accesses to enabled mem-
Up/Down Count Mismatch Detection
ory regions only. A supervisor mode vs. user mode The GP counter can monitor external signal pairs, such as programming model supports dynamically varying access request/grant strobes. If the edge count mismatch exceeds the rights. Increased flexibility in memory page size options sup- expected range, the GP counter can flag this to the processor or ports a simple method of static memory partitioning. to the fault management unit of the SEC.
System Protection Fault Management
The system protection unit (SPU) guards against accidental or The fault management unit is part of the system event controller unwanted access to the MMR space of a peripheral by providing (SEC). Any system event, whether a dual-bit uncorrectable ECC a write-protection mechanism. The user is able to choose and error, or any peripheral status interrupt, can be defined as being configure the peripherals that are protected as well as configure a fault. Additionally, the system events can be defined as an which ones of the four system MMR masters (core, memory interrupt to the core. If defined as such, the SEC forwards the DMA, the SPI host port, and Coresight debug) the peripherals event to the fault management unit, which may automatically are guarded against. reset the entire device for reboot, or simply toggle the  The SPU is also part of the security infrastructure. Along with SYS_FAULT output pin to signal off-chip hardware. Optionally, providing write-protection functionality, the SPU is employed the fault management unit can delay the action taken through a to define which resources in the system are secure or non-secure keyed sequence, to provide a final chance for the Blackfin+ core and to block access to secure resources from non-secure to resolve the issue and to prevent the fault action from being masters. taken. Rev. D | Page 9 of 114 | February 2019 Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide