Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices) - 3

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ADSP-BF700/701/702/703/704/705/706/707 GENERAL DESCRIPTION
The ADSP-BF70x processor is a member of the Blackfin®  The processor offers performance up to 400 MHz, as well as low family of products. The Blackfin processor combines a dual- static power consumption. Produced with a low-power and low- MAC 16-bit state-of-the-art signal processing engine, the voltage design methodology, they provide world-class power advantages of a clean, orthogonal RISC-like microprocessor management and performance. instruction set, and single-instruction, multiple-data (SIMD) By integrating a rich set of industry-leading system peripherals multimedia capabilities into a single instruction-set architec- and memory (shown in Table 1), the Blackfin processor is the ture. New enhancements to the Blackfin+ core add 32-bit MAC platform of choice for next-generation applications that require and 16-bit complex MAC support, cache enhancements, branch RISC-like programmability, multimedia support, and leading- prediction and other instruction set improvements—all while edge signal processing in one integrated package. These applica- maintaining instruction set compatibility to previous Blackfin tions span a wide array of markets, from automotive systems to products. embedded industrial, instrumentation, video/image analysis, biometric and power/motor control applications.
Table 1. Processor Comparison ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- Processor Feature BF700 BF701 BF702 BF703 BF704 BF705 BF706 BF707
Maximum Speed Grade (MHz)1 200 400 Maximum SYSCLK (MHz) 100 200 Package Options 88-Lead 184-Ball 88-Lead 184-Ball 88-Lead 184-Ball 88-Lead 184-Ball LFCSP CSP_BGA LFCSP CSP_BGA LFCSP CSP_BGA LFCSP CSP_BGA GPIOs 43 47 43 47 43 47 43 47 L1 Instruction SRAM 48K L1 Instruction SRAM/Cache 16K L1 Data SRAM 32K (bytes) L1 Data SRAM/Cache 32K y L1 Scratchpad (L1 Data C) 8K mor e L2 SRAM 128K 256K 512K 1024K M L2 ROM 512K DDR2/LPDDR (16-bit) No Yes No Yes No Yes No Yes I2C 1 Up/Down/Rotary Counter 1 GP Timer 8 Watchdog Timer 1 GP Counter 1 SPORTs 2 Quad SPI 2 Dual SPI 1 SPI Host Port 1 USB 2.0 HS OTG 1 Parallel Peripheral Interface 1 CAN 2 UART 2 Real-Time Clock 1 Static Memory Controller (SMC) Yes Security Crypto Engine Yes SD/SDIO (MSI) 4-bit 8-bit 4-bit 8-bit 4-bit 8-bit 4-bit 8-bit 4 -Channel 12-Bit ADC No Yes No Yes No Yes No Yes 1 Other speed grades available. Rev. D | Page 3 of 114 | February 2019 Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide