Datasheet ADCMP580, ADCMP581, ADCMP582 (Analog Devices) - 5

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Data Sheet ADCMP580/ADCMP581/ADCMP582 TIMING INFORMATION
Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the terms shown in Figure 2.
LATCH ENABLE 50% LATCH ENABLE tS tPL tH DIFFERENTIAL VN VN ± VOS INPUT VOLTAGE VOD tPDL tPLOH Q OUTPUT 50% tF tPDH 50% Q OUTPUT tPLOL
002
tR
04672- Figure 2. Comparator Timing Diagram
Table 2. Timing Descriptions Symbol Symbol Description Timing Description
tPDH Input-to-Output High Delay Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition. tPDL Input-to-Output Low Delay Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition. tPLOH Latch Enable-to-Output High Delay Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. tPLOL Latch Enable-to-Output Low Delay Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. tH Minimum Hold Time Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. tPL Minimum Latch Enable Pulse Width Minimum time that the latch enable signal must be high to acquire an input signal change. tS Minimum Setup Time Minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs. tR Output Rise Time Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. tF Output Fall Time Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. VN Normal Input Voltage Difference between the input voltages VP and VN for output true. VOD Voltage Overdrive Difference between the input voltages VP and VN for output false. Rev. B | Page 5 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL APPLICATION CIRCUITS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING ADCMP580/ADCMP581/ADCMP582 FAMILY OF OUTPUT STAGES USING/DISABLING THE LATCH FEATURE OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT OUTLINE DIMENSIONS ORDERING GUIDE NOTES