Datasheet ADCMP580, ADCMP581, ADCMP582 (Analog Devices)

Ultrafast SiGe Voltage Comparators Data Sheet ADCMP580/ ADCMP581 /ADCMP582 FEATURES FUNCTIONAL BLOCK DIAGRAM 180 ps propagation delay VCCI 25 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth VTP TERMINATION VCCO 100 ps minimum pulse width V 37 ps typical output rise/fall P NONINVERTING INPUT ADCMP580/ Q OUTPUT 10 ps deterministic jitter (DJ) ADCMP581/ CML/ECL/ 200 fs random jitter (RJ) ADCMP582 PECL Q OUTPUT V −2 V to +3 V input range with +5 V/−5 V supplies N INVERTING INPUT On-chip terminations at both input pins V Resistor-programmable hysteresis V EE TN TERMINATION Differential latch control LE INPUT Power supply rejection > 70 dB HYS LE INPUT
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APPLICATIONS VEE
04672- Figure 1.
Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration GENERAL DESCRIPTION
The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage The CML output stage is designed to directly drive 400 mV into comparators fabricated on the Analog Devices, Inc. proprietary 50 Ω transmission lines terminated to ground. The NECL output XFCB3 Silicon Germanium (SiGe) bipolar process. The stages are designed to directly drive 400 mV into 50 Ω terminated ADCMP580 features CML output drivers, the ADCMP581 to −2 V. The PECL output stages are designed to directly drive features reduced swing ECL (negative ECL) output drivers, and 400 mV into 50 Ω terminated to VCCO − 2 V. High speed latch the ADCMP582 features reduced swing PECL (positive ECL) and programmable hysteresis are also provided. The differential output drivers. latch input controls are also 50 Ω terminated to an independent All three comparators offer 180 ps propagation delay and 100 ps VTT pin to interface to either CML or ECL or to PECL logic. minimum pulse width for 10 Gbps operation with 200 fs random The ADCMP580/ADCMP581/ADCMP582 are available in a jitter (RJ). Overdrive and slew rate dispersion are typically less 16-lead LFCSP. than 15 ps. The ±5 V power supplies enable a wide −2 V to +3 V input range with logic levels referenced to the CML/NECL/PECL outputs. The inputs have 50 Ω on-chip termination resistors with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance input.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL APPLICATION CIRCUITS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING ADCMP580/ADCMP581/ADCMP582 FAMILY OF OUTPUT STAGES USING/DISABLING THE LATCH FEATURE OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT OUTLINE DIMENSIONS ORDERING GUIDE NOTES