Datasheet ADCMP606, ADCMP607 (Analog Devices) - 10

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ADCMP606/ADCMP607 Data Sheet APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING
If these high speed signals must be routed more than a centimeter, The ADCMP606/ADCMP607 comparators are very high speed then either microstrip or strip line techniques are required to devices. Despite the low noise output stage, it is essential to use ensure proper transition times and to prevent excessive output proper high speed design techniques to achieve the specified ringing and pulse width dependent propagation delay performance. Because comparators are uncompensated amplifiers, dispersion. feedback in any phase relationship is likely to cause oscil ations It is also possible to operate the outputs with the internal or undesired hysteresis. Of critical importance is the use of low termination only if greater output swing is desired. This can be impedance supply planes, particularly the output supply plane especially useful for driving inputs on CMOS devices intended (VCCO) and the ground plane (GND). Individual supply planes for ful swing ECL and PECL, or for generating pseudo PECL are recommended as part of a multilayer board. Providing the levels. To avoid deep saturation of the outputs and resulting lowest inductance return path for switching currents ensures pulse dispersion, VCCO must be kept above the specified minimum the best possible performance in the target application. output low level (see the Electrical Characteristics section). The It is also important to adequately bypass the input and output line length driven should be kept as short as possible. supplies. Multiple high quality 0.01 µF bypass capacitors should
USING/DISABLING THE LATCH FEATURE
be placed as close as possible to each of the VCCI and VCCO supply The latch input is designed for maximum versatility. It can pins and should be connected to the GND plane with redundant safely be left floating or it can be driven low by any standard vias. At least one of these should be placed to provide a physical y TTL/CMOS device as a high speed latch. short return path for output currents flowing back from ground to the V In addition, the pin can be operated as a hysteresis control pin CCI and VCCO pins. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. with a bias voltage of 1.25 V nominal and an input resistance of Parasitic layout inductance should also be strictly controlled to approximately 70 kΩ. This allows the comparator hysteresis to maximize the effectiveness of the bypass at high frequencies. be easily controlled by either a resistor or an inexpensive CMOS DAC. Driving this pin high or floating the pin removes al
CML-COMPATIBLE OUTPUT STAGE
hysteresis. Specified propagation delay dispersion performance can be Hysteresis control and latch mode can be used together if an achieved by using proper transmission line terminations. The open-drain, an open-collector, or a three-state driver is connected outputs of the ADCMP606 and ADCMP607 are designed to drive parallel to the hysteresis control resistor or current source. 400 mV directly into a 50 Ω cable or into transmission lines terminated using either microstrip or strip line techniques with Due to the programmable hysteresis feature, the logic threshold 50 Ω referenced to V of the latch pin is approximately 1.1 V regardless of VCCO. CCO. The CML output stage is shown in the simplified schematic diagram in Figure 14. Each output is back
OPTIMIZING PERFORMANCE
terminated with 50 Ω for best transmission line matching. As with any high speed comparator, proper design and layout
VCCO
techniques are essential for obtaining the specified performance. Stray capacitance, inductance, inductive power and ground
50Ω
impedances, or other layout issues can severely limit performance and often cause oscillation. Large discontinuities along input
Q
and output transmission lines can also limit the specified pulse width dispersion performance. The source impedance should
Q
be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at
16mA
the input, thus degrading the overall response. Thermal noise from large resistances can easily cause extra jitter with slowly 013
GND
slewing input signals; higher impedances encourage undesired 05917- Figure 14. Simplified Schematic Diagram of coupling. CML-Compatible Output Stage Rev. C | Page 10 of 14 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE