Datasheet ADCMP606, ADCMP607 (Analog Devices)

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators Data Sheet ADCMP606/ ADCMP607 FEATURES GENERAL DESCRIPTION Fully specified rail to rail at VCCI = 2.5 V to 5.5 V
The ADCMP606 and ADCMP607 are very fast comparators
Input common-mode voltage from −0.2 V to VCCI + 0.2 V
fabricated on XFCB2, an Analog Devices, Inc., proprietary
CML-compatible output stage
process. These comparators are exceptionally versatile and easy
1.25 ns propagation delay
to use. Features include an input range from VEE − 0.5 V to
50 mW at 2.5 V power supply
VCCI + 0.2 V, low noise, CML-compatible output drivers, and
Shutdown pin
TTL-/CMOS-compatible latch inputs with adjustable hysteresis
Single-pin control for programmable hysteresis and latch
and/or shutdown inputs.
(ADCMP607 on ly)
The devices offer 1.25 ns propagation delay with 2.5 ps rms
Power supply rejection > 60 dB
random jitter (RJ). Overdrive and slew rate dispersion are
−40°C to +125°C operation
typically less than 50 ps.
APPLICATIONS
A flexible power supply scheme al ows the devices to operate
High speed instrumentation
with a single +2.5 V positive supply and a −0.5 V to +2.7 V
Clock and data signal restoration
input signal range up to a +5.5 V positive supply with a −0.5 V
Logic level shifting or translation
to +5.7 V input signal range. The ADCMP607 features split
Pulse spectroscopy
input/output supplies with no sequencing restrictions to
High speed line receivers
support a wide input signal range with independent output
Threshold detection
swing control and power savings.
Peak and zero-crossing detectors
The CML-compatible output stage is ful y back-matched for
High speed trigger circuitry
superior performance. The comparator input stage offers robust
Pulse-width modulators
protection against large input overdrive, and the outputs do not
Current-/voltage-controlled oscillators
phase reverse when the valid input signal range is exceeded. On
Automatic test equipment (ATE)
the ADCMP607, latch and programmable hysteresis features are also provided with a unique single-pin control option. The ADCMP606 is available in a 6-lead SC70 package and the ADCMP607 is available in a 12-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM VCCO VCCI (ADCMP607 ONLY) VP NONINVERTING INPUT Q OUTPUT ADCMP606/ CML ADCMP607 Q OUTPUT VN INVERTING INPUT LE/HYS INPUT (ADCMP607 ONLY)
001
SDN INPUT (ADCMP607 ONLY)
05917- Figure 1.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE