Data SheetADCMP606/ADCMP607SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = −40°C to +125°C, typical at TA = 25°C, unless otherwise noted. Table 1. ParameterSymbolTest Conditions/Comments MinTypMaxUnit DC INPUT CHARACTERISTICS Voltage Range VP, VN VCCI = 2.5 V to 5.5 V −0.5 VCCI + 0.2 V Common-Mode Range VCCI = 2.5 V to 5.5 V −0.2 VCCI + 0.2 V Differential Voltage VCCI = 2.5 V to 5.5 V VCCI V Offset Voltage VOS −5.0 +5.0 mV Bias Current IP, IN −5.0 ±2 +5.0 µA Offset Current −2.0 2.0 µA Capacitance CP, CN 1 pF Resistance, Differential Mode −0.1 V to VCCI 200 700 kΩ Resistance, Common Mode −0.5 V to VCCI + 0.5 V 100 350 kΩ Active Gain AV 85 dB Common-Mode Rejection Ratio CMRR VCCI = 2.5 V, VCCO = 2.5 V, 50 dB VCM = −0.2 V to +2.7 V VCCI = 2..5 V, VCCO = 5.5 V 50 dB Hysteresis RHYS = ∞ <0.1 mV LATCH ENABLE PIN CHARACTERISTICS (ADCMP607 Only) VIH Hysteresis is shut off 2.0 VCCO V VIL Latch mode guaranteed −0.2 +0.4 +0.8 V IIH VIH = VCCO −6 +6 µA IIL VIL = 0.4 V −0.1 +0.1 mA HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Current sink 0 µA 1.145 1.25 1.35 V Minimum Resistor Value Hysteresis = 120 mV 55 75 110 kΩ Latch Setup Time tS VOD = 50 mV −1.5 ns Latch Hold Time tH VOD = 50 mV 2.3 ns Latch-to-Output Delay tPLOH, tPLOL VOD = 50 mV 30 ns Latch Minimum Pulse Width tPL VOD = 50 mV 25 ns SHUTDOWN PIN CHARACTERISTICS (ADCMP607 Only) VIH Comparator is operating 2.0 VCCO V VIL Shutdown guaranteed −0.2 +0.4 +0.6 V IIH VIH = VCCO −6 +6 µA IIL VIL = 0 V −0.1 mA Sleep Time tSD 10% output swing <1 ns Wake-Up Time tH VOD = 100 mV, output valid 35 ns DC OUTPUT CHARACTERISTICS VCCO = 2.5 V to 5.5 V Output Voltage High Level VOH 50 Ω terminate to VCCO VCCO − 0.1 VCCO − 0.05 VCCO V Output Voltage Low Level VOL 50 Ω terminate to VCCO VCCO − 0.6 VCCO − 0.45 VCCO − 0.3 V Output Voltage Differential 50 Ω terminate to VCCO 300 400 500 mV Rev. C | Page 3 of 14 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE