Datasheet ADN8835 (Analog Devices) - 7

Data Sheet ADN8835 ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL RESISTANCE Parameter Rating
θJA is specified for the worst-case conditions, that is, a device PVINL to PGNDL −0.3 V to +6 V soldered in a circuit board for surface-mount packages, and is PVINS to PGNDS −0.3 V to +6 V based on a 4-layer standard JEDEC board. LDR to PGNDL −0.3 V to VPVINL
Table 4. Thermal Resistance
SW to PGNDS −0.3 V to +6 V SFB to AGND −0.3 V to V
Package Type θJA ΨJT ΨJB Unit
VDD AGND to PGNDL −0.3 V to +0.3 V 36-Lead LFCSP 33 1.2 12.3 °C/W AGND to PGNDS −0.3 V to +0.3 V
MAXIMUM POWER DISSIPATION
VLIM/SD to AGND −0.3 V to VVDD ILIM to AGND −0.3 V to V The maximum power that the ADN8835 can dissipate is limited VDD VREF to AGND −0.3 V to +3 V by the associated rise in junction temperature. The maximum VDD to AGND −0.3 V to +6 V safe junction temperature for a plastic encapsulated device is IN1P to AGND −0.3 V to V determined by the glass transition temperature of the plastic, VDD IN1N to AGND −0.3 V to V approximately 125°C. Exceeding this limit may cause a shift in VDD OUT1 to AGND −0.3 V to +6 V parametric performance or device failure. IN2P to AGND −0.3 V to VVDD The driver stage of the ADN8835 is designed for maximum IN2N to AGND −0.3 V to VVDD load current capability. To ensure proper operation, it is OUT2 to AGND −0.3 V to +6 V necessary to observe the corresponding maximum power EN/SY to AGND −0.3 V to VVDD derating curves. ITEC to AGND −0.3 V to +6 V
3.5
VTEC to AGND −0.3 V to +6 V
TJ = 125°C )
Maximum Current
3.0 (W
VREF to AGND 20 mA
N IO 2.5 T
OUT1 to AGND 50 mA
PA
OUT2 to AGND 50 mA
ISSI 2.0 D
ITEC to AGND 50 mA
ER W 1.5
VTEC to AGND 50 mA Junction Temperature 125°C
M PO 1.0 MU
Storage Temperature Range −65°C to +150°C
XI
Lead Temperature (Soldering, 10 sec) 260°C
MA 0.5
Stresses at or above those listed under Absolute Maximum
0 30 40 50 60 70 80
003 Ratings may cause permanent damage to the product. This is a
AMBIENT TEMPERATURE (°C)
14174- stress rating only; functional operation of the product at these Figure 3. Maximum Power Dissipation vs. Ambient Temperature or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may
ESD CAUTION
affect product reliability. Rev. B | Page 7 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG PID CONTROL DIGITAL PID CONTROL POWERING THE CONTROLLER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8835 Devices TEMPERATURE LOCK INDICATOR SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION SIGNAL FLOW THERMISTOR SETUP THERMISTOR AMPLIFIER (CHOPPER 1) PID COMPENSATION AMPLIFIER (CHOPPER 2) MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Losses (PSW) Transition Losses (PTRAN) Linear Regulator Power Dissipation THERMAL CONSIDERATION PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE