Datasheet ADN8835 (Analog Devices) - 6

ADN8835 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Voltage Measurement Accuracy VVTEC_AT_1_V VLDR − VSFB = 1 V, VVREF/2 + AVTEC × 1.475 1.50 1.525 V (VLDR − VSFB) VTEC Output Voltage Range VVTEC 0.005 2.625 V VTEC Bias Voltage VVTEC_B VLDR = VSFB 1.225 1.250 1.285 V Maximum VTEC Output Current RVTEC −2 +2 mA TEMPERATURE GOOD TMPGD Output Voltage No load Low VTMPGD_LO 0.4 V High VTMPGD_HO 2.0 V TMPGD Output Impedance Low RTMPGD_LOW 25 Ω High RTMPGD_LOW 50 Ω Threshold IN2N tied to OUT2, VIN2P = 1.5 V High VOUT1_THH 1.54 1.56 V Low VOUT1_THL 1.40 1.46 V INTERNAL SOFT START Soft Start Time tSS 150 ms VLIM/SD SHUTDOWN Low Voltage Threshold VVLIM/SD_THL 0.07 V THERMAL SHUTDOWN Threshold TSHDN_TH 170 °C Hysteresis TSHDN_HYS 17 °C 1 This specification is guaranteed by design. 2 This specification is guaranteed by characterization. Rev. B | Page 6 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG PID CONTROL DIGITAL PID CONTROL POWERING THE CONTROLLER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8835 Devices TEMPERATURE LOCK INDICATOR SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION SIGNAL FLOW THERMISTOR SETUP THERMISTOR AMPLIFIER (CHOPPER 1) PID COMPENSATION AMPLIFIER (CHOPPER 2) MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Losses (PSW) Transition Losses (PTRAN) Linear Regulator Power Dissipation THERMAL CONSIDERATION PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE