Datasheet ADN8835 (Analog Devices) - 8

ADN8835 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D T1 NDL NDL MPG G G DNC DNC IN2P IN1P IN1N OU T P P 36 35 34 33 32 31 30 29 28 DNC 1 27 LDR DNC 2 26 LDR IN2N 3 25 PVINL OUT2 4 24 PVINL ADN8835 VLIM/SD 5 23 PVINS TOP VIEW ILIM 6 (Not to Scale) 22 PVINS VDD 7 21 SW VREF 8 20 SW DNC 9 19 DNC 10 11 12 13 14 15 16 17 18 B C ND /SY EC DNC DNC SF ITE NDS NDS AG EN VT G G P P NOTES 1. DO NOT CONNECT. LEAVE THESE PINS PIN FLOATING.
004
2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE ANALOG GROUND PLANE ON THE BOARD.
14174- Figure 4. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
0 EPAD Exposed Pad. Solder the exposed pad to the analog ground plane on the board. 1, 2, 9, 10, 11, 19, DNC Do Not Connect. Leave these pins floating. 35, 36 3 IN2N Inverting Input of the Compensation Amplifier. 4 OUT2 Output of the Compensation Amplifier. 5 VLIM/SD Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage limits. When this pin is pul ed low, the device shuts down. 6 ILIM Current Limit. This pin sets the TEC cooling and heating current limits. 7 VDD Power for the Control er Circuits. 8 VREF 2.5 V Reference Output. 12 AGND Signal Ground. 13 EN/SY Enable/Synchronization. Set this pin high to enable the device. An external synchronization clock input can be applied to this pin. 14 VTEC TEC Voltage Output. 15 SFB Feedback of the PWM TEC Controller Output. 16 ITEC TEC Current Output. 17, 18 PGNDS Power Ground of the PWM TEC Controller. 20, 21 SW Switch Node Output of the PWM TEC Controller. 22, 23 PVINS Power Input for the PWM TEC Driver. 24, 25 PVINL Power Input for the Linear TEC Driver. 26, 27 LDR Output of the Linear TEC Controller. 28, 29 PGNDL Power Ground of the Linear TEC Controller. 30 TMPGD Temperature Good Output. 31 OUT1 Output of the Error Amplifier. 32 IN1N Inverting Input of the Error Amplifier. 33 IN1P Noninverting Input of the Error Amplifier. 34 IN2P Noninverting Input of the Compensation Amplifier. Rev. B | Page 8 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG PID CONTROL DIGITAL PID CONTROL POWERING THE CONTROLLER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8835 Devices TEMPERATURE LOCK INDICATOR SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION SIGNAL FLOW THERMISTOR SETUP THERMISTOR AMPLIFIER (CHOPPER 1) PID COMPENSATION AMPLIFIER (CHOPPER 2) MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Losses (PSW) Transition Losses (PTRAN) Linear Regulator Power Dissipation THERMAL CONSIDERATION PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE