Datasheet KSZ8895MQX, KSZ8895RQX KSZ8895FQX, KSZ8895MLX (Microchip) - 6
| Fabricante | Microchip |
| Descripción | Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface |
| Páginas / Página | 109 / 6 — KSZ8895MQX/RQX/FQX/MLX. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE … |
| Formato / tamaño de archivo | PDF / 2.8 Mb |
| Idioma del documento | Inglés |
KSZ8895MQX/RQX/FQX/MLX. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. 128-PQFP PIN ASSIGNMENT (TOP VIEW)
Línea de modelo para esta hoja de datos
- KSZ8895FQXC KSZ8895FQXC-TR KSZ8895FQXCA KSZ8895FQXI KSZ8895FQXI-TR KSZ8895FQXIA KSZ8895ML KSZ8895MLUB KSZ8895MLUB-TR KSZ8895MLXC KSZ8895MLXC-TR KSZ8895MLXI KSZ8895MLXI-TR KSZ8895MQ KSZ8895MQI KSZ8895MQXC KSZ8895MQXC-TR KSZ8895MQXCA KSZ8895MQXI KSZ8895MQXI-TR KSZ8895MQXIA KSZ8895RQI KSZ8895RQXC KSZ8895RQXC-TR KSZ8895RQXCA KSZ8895RQXCA-TR KSZ8895RQXI KSZ8895RQXI-TR KSZ8895RQXIA SPNY801156 SPNY801159 SPNY801159-TR SPNY801160 SPNY801160-TR SPNY801171 SPNY801172 SPNY801172-TR SPNZ801156 SPNZ801159 SPNZ801159-TR SPNZ801160 SPNZ801160-TR SPNZ801161 SPNZ801171 SPNZ801172
Versión de texto del documento
KSZ8895MQX/RQX/FQX/MLX 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: 128-PQFP PIN ASSIGNMENT (TOP VIEW)
LED2-1 LED2-2 VDDIO GNDD LED3-0 LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 VDDC GNDD SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV/SMCRSDV SMRXC VDDIO GNDD SMTXC/SMREFCLK SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN PCOL PCRS PMRXER PMRXD0 101 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 102 100 99 98 97 103 64 PMRXD1 LED2-0 63 PMRXD2 LED1-2 104 105 62 PMRXD3 LED1-1 106 61 PMRXDV/PMCRSDV LED1-0 107 60 PMRXC MDC 108 59 VDDIO MDIO 109 58 GNDD SPIQ 110 57 PMTXC/PMREFCLK SPIC/SCL 111 56 PMTXER SPID/SDA SPIS_N 112 PS1 113 114
KSZ8895MQX/RQX/FQX
55 PMTXD0 54 PMTXD1 53 PMTXD2 PS0 115 52 PMTXD3 RST_N 116 51 PMTXEN GNDD VDDC 117 TESTEN 118 119 50 VDDC 49 GNDD 48 INTR_N SCANEN 120 47 PWRDN_N NC 121 46 X1 X2 122
(Top View)
NC 45 NC 123 44 NC NC NC 124 43 NC 125 42 NC LDO_O 126 41 NC IN_PWR_SEL 127 40 NC GNDA 128 39 FXSD4 TEST2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 T T T T RXP1 RXM1 TXP1 TXM1 RXP2 TXP2 TXM2 ISET RXP3 TXP5 RXM2 GNDA GNDA RXM3 TXP3 RXP4 RXM4 TXM4 GNDA TXM3 GNDA TXP4 GNDA RXP5 RXM5 TXM5 GNDA GNDA GNDA VDDA VDDA VDDA VDDA FXSD3 VDDAR VDDAR VDDAR MDIXDIS DS00002246B-page 6 2016 - 2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
LED2-1 LED2-2 VDDIO GNDD LED3-0 LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 VDDC GNDD SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV/SMCRSDV SMRXC VDDIO GNDD SMTXC/SMREFCLK SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN PCOL PCRS PMRXER PMRXD0 101 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 102 100 99 98 97 103 64 PMRXD1 LED2-0 63 PMRXD2 LED1-2 104 105 62 PMRXD3 LED1-1 106 61 PMRXDV/PMCRSDV LED1-0 107 60 PMRXC MDC 108 59 VDDIO MDIO 109 58 GNDD SPIQ 110 57 PMTXC/PMREFCLK SPIC/SCL 111 56 PMTXER SPID/SDA SPIS_N 112 PS1 113 114
KSZ8895MQX/RQX/FQX
55 PMTXD0 54 PMTXD1 53 PMTXD2 PS0 115 52 PMTXD3 RST_N 116 51 PMTXEN GNDD VDDC 117 TESTEN 118 119 50 VDDC 49 GNDD 48 INTR_N SCANEN 120 47 PWRDN_N NC 121 46 X1 X2 122
(Top View)
NC 45 NC 123 44 NC NC NC 124 43 NC 125 42 NC LDO_O 126 41 NC IN_PWR_SEL 127 40 NC GNDA 128 39 FXSD4 TEST2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 T T T T RXP1 RXM1 TXP1 TXM1 RXP2 TXP2 TXM2 ISET RXP3 TXP5 RXM2 GNDA GNDA RXM3 TXP3 RXP4 RXM4 TXM4 GNDA TXM3 GNDA TXP4 GNDA RXP5 RXM5 TXM5 GNDA GNDA GNDA VDDA VDDA VDDA VDDA FXSD3 VDDAR VDDAR VDDAR MDIXDIS DS00002246B-page 6 2016 - 2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service