Datasheet KSZ8895MQX, KSZ8895RQX KSZ8895FQX, KSZ8895MLX (Microchip) - 10

KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Type, Pin Pin Note Port Pin Function, Note 2-2 Number Name 2-1
59 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. MQX/FQX/MLX: Output PHY [5] MII receive clock. RQX: Output PHY [5] RMII reference clock, this clock is used when 60 PMRXC I/O 5 opposite doesn’t provide RMII 50 MHz clock or the system doesn’t provide an external 50 MHz clock for the P5-RMII interface. MQX/FQX/MLX: PMRXDV is for PHY [5] MII receive data valid. PMRXDV/ 61 IPD/O 5 RQX: PMCRSDV is for PHY [5] RMII Carrier Sense/Receive Data PMCRSDV Valid Output. MQX/FQX/MLX: PHY [5] MII receive bit 3. RQX: no connection for RMII. 62 PMRXD3 IPD/O 5 Strap option: PD (default) = enable flow control. PU = disable flow control. MQX/FQX/MLX: PHY [5] MII receive bit 2. RQX: no connection for RMII. 63 PMRXD2 IPD/O 5 Strap option: PD (default) = disable back pressure. PU = enable back pressure. MQX/FQX/MLX: PHY [5] MII receive bit 1. RQX: PHY [5] RMII receive bit 1. 64 PMRXD1 IPD/O 5 Strap option: PD (default) = drop excessive collision packets. PU = does not drop excessive collision packets. MQX/FQX/MLX: PHY [5] MII receive bit 0. RQX: PHY [5] RMII receive bit 0. Strap option: 65 PMRXD0 IPD/O 5 PD (default) = disable aggressive back-off algorithm in half-duplex mode. PU = enable for performance enhancement. MQX/FQX/MLX:PHY [5] MII receive error RQX: PHY [5] RMII receive error 66 PMRXER IPD/O 5 Strap option: PD (default) = packet size 1518/1522 bytes. PU = 1536 bytes. MQX/FQX/MLX: PHY [5] MII carrier sense. RQX: no connection for RMII. Strap option for port 4 only. 67 PCRS IPD/O 5 PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto negotiation is disabled or fails. Refer to Register 76. MQX/FQX/MLX: PHY [5] MII collision detect. RQX: no connection. 68 PCOL IPD/O 5 Strap option for port 4 only. PD (default) = no force flow control, normal operation. PU = force flow control. Refer to Register 66. DS00002246B-page 10  2016 - 2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service