Datasheet KSZ8895MQX, KSZ8895RQX KSZ8895FQX, KSZ8895MLX (Microchip) - 5

KSZ8895MQX/RQX/FQX/MLX 1.0 INTRODUCTION 1.1 General Description
The KSZ8895MQX/RQX/FQX/MLX is a highly-integrated, Layer 2 managed, five-port switch with numerous features designed to reduce system cost. Intended for cost-sensitive 10/100Mbps five-port switch systems with low power con- sumption, on-chip termination, and internal core power controllers, it supports high-performance memory bandwidth and shared memory-based switch fabric with non-blocking configuration. Its extensive feature set includes power manage- ment, programmable rate limit and priority ratio, tag/port-based VLAN, packets filtering, four-queue QoS prioritization, management interfaces, and MIB counters. The KSZ8895 family provides multiple CPU data interfaces to effectively address both current and emerging fast Ethernet applications when Port 5 is configured to separate MAC5 with SW5- MII/RMII and PHY5 with P5-MII/RMII interfaces. The KSZ8895 family offers three configurations, providing the flexibility to meet different requirements: • KSZ8895MQX/MLX: Five 10/100Base-T/TX transceivers, One SW5-MII, and One P5-MII interface • KSZ8895RQX: Five 10/100Base-T/TX transceivers, One SW5-RMII, and One P5-RMII interface • KSZ8895FQX: Four 10/100Base-T/TX transceivers on Ports 1, 2, 3, and 5 (port 3 can be set to fiber mode). One 100Base-FX transceiver on Port 4. One SW5-MII and One P5-MII interface All registers of MACs and PHYs units can be managed by the SPI or the SMI interface. MIIM registers can be accessed through the MDC/MDIO interface. EEPROM can set all control registers for the unmanaged mode. KSZ8895MQX/RQX/FQX are available in the 128-pin PQFP package. KSZ8895MLX is available as a 128-pin LQFP package.
FIGURE 1-1: FUNCTIONAL DIAGRAM KSZ8895MQX/RQX/FQX/MLX
10/100 10/100 FIFO, FLOW CONTROL, VLAN TAGGING, PROIRITY LOOK UP AUTOMDI/MDIX T/TX MAC1 ENGINE PHY1 10/100 10/100 AUTOMDI/MDIX T/TX QUEUE MAC2 PHY2 MANAGEMENT 10/100 10/100 AUTOMDI/MDIX T/TX/FX MAC3 BUFFER PHY3 MANAGEMENT 10/100 10/100 AUTOMDI/MDIX T/TX/FX MAC4 PHY4 FRAME BUFFERS AUTOMDI/MDIX 10/100 10/100 T/TX MAC5 PHY5 P5-MII/RMII MIB MDC/MDIO FOR MIIM AND SMI COUNTERS SW5-MII/RMII OR SNI CONTROL REG SPI I/F SPI EEPROM LED LED I/F LED CONTROL INTERFACE LED REGISTERS  2016 - 2019 Microchip Technology Inc. DS00002246B-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service