Datasheet KSZ8852HLE (Microchip) - 9

KSZ8852HLE 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: 64-PIN LQFP ASSIGNMENT, (TOP VIEW)
N/U RSTN P2LED0/LEBE P2LED1 P1LED0/H816 P1LED1 N/U DGND VDD_IO EECS EEDIO EESK N/U VDD_L DGND N/U 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RXM1 1 48 N/U RXP1 2 47 CSN AGND 3 46 PME/EEPROM TXM1 4 45 WRN TXP1 5 44 RDN VDD_AL 6 43 INTRN ISET 7 42 CMD
KSZ8852HLE
AGND 8 41 SD0 VDD_A3.3 9 40 VDD_L RXM2 10 39 DGND RXP2 11 38 SD1 AGND 12 37 SD2 13 36 TXM2 SD3 14 35 TXP2 SD4 34 N/U 15 SD5 33 VDD_COL 16 SD6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 X1 X2 SD9 SD8 SD7 DGND SD15 SD14 SD13 SD12 SD1 SD10 DGND PWRDN VDD_IO VDD_IO  2018 Microchip Technology Inc. DS00002761A-page 9 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 MDI/MDI−X Auto Crossover 3.4 Auto Negotiation 3.5 LINK MD® Cable Diagnostics 3.6 On-Chip Termination Resistors 3.7 Lookback Support 3.8 MAC (Media Access Controller) Block 3.9 Switch Block 3.10 IGMP Support 3.11 IPv6 MLD Snooping 3.12 Port Mirroring Support 3.13 IEEE 802.1Q VLAN Support 3.14 QoS Priority Support 3.15 Rate-Limiting Support 3.16 MAC Address Filtering Function 3.17 Queue Management Unit (QMU) 3.18 Device Clocks 3.19 Power 3.20 Internal Low Voltage LDO Regulator 3.21 Power Management 3.22 Wake-On-LAN 3.23 Interfaces 4.0 Register Descriptions 4.1 Device Registers 4.2 Register Map of CPU Accessible I/O Registers 4.3 Register Bit Definitions 4.4 Type-of-Service (TOS) Priority Control Registers 4.5 Indirect Access Data Registers 4.6 Power Management Control and Wake-Up Event Status 4.7 Go Sleep Time and Clock Tree Power-Down Control Registers 4.8 PHY and MII Basic Control Registers 4.9 Port 1 Control Registers 4.10 Port 2 Control Registers 4.11 Port 3 Control Registers 4.12 Switch Global Control Registers 4.13 Source Address Filtering Registers 4.14 TXQ Rate Control Registers 4.15 Auto-Negotiation Next Page Registers 4.16 EEE and Link Partner Advertisement Registers 4.17 Internal I/O Register Space Mapping for Interrupts, BIU, and Global Reset (0x100 - 0x1FF) 4.18 Host MAC Address Registers: MARL, MARM, and MARH 4.19 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x170 - 0x1FF) 4.20 Internal I/O Register Space Mapping for Interrupt Registers (0x190 - 0x193) 4.21 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x19C - 0x1B9) 4.22 Management Information Base (MIB) Counters 4.23 Static MAC Address Table 4.24 Dynamic MAC Address Table 4.25 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read / Write Timing 7.2 Auto-Negotiation Timing 7.3 Serial EEPROM Interface Timing 7.4 Reset Timing and Power Sequencing 7.5 Reset Circuit Guidelines 7.6 Reference Circuits – LED Strap-In Pins 7.7 Reference Clock – Connection and Selection 8.0 Selection of Isolation Transformers 9.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service