Datasheet KSZ8852HLE (Microchip) - 2
| Fabricante | Microchip |
| Descripción | Two-Port 10/100 Ethernet Switch with 8-/16-Bit Host Interface Features |
| Páginas / Página | 170 / 2 — KSZ8852HLE. Applications. Power and Power Management. Additional … |
| Formato / tamaño de archivo | PDF / 2.1 Mb |
| Idioma del documento | Inglés |
KSZ8852HLE. Applications. Power and Power Management. Additional Features. Packaging
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KSZ8852HLE
Marks for Flow Control in RX FIFO
Applications
• Efficient Architecture Design with Configurable Host Interrupt Schemes to Minimize Host CPU • General and Industrial Ethernet Applications Overhead and Utilization • Wireless LAN Access Point and Gateway • Queue Management Unit (QMU) Supervises Data • Set Top / Game Box Transfers Across this Interface • Test and Measurement Equipment
Power and Power Management
• Automotive • Single 3.3V Power Supply with Optional VDD I/O for 1.8V, 2.5V, or 3.3V • Integrated Low-Voltage (~1.3V) Low-Noise Regulator (LDO) Output for Digital and Analog Core Power • Supports IEEE P802.3az™ Energy Efficient Ethernet (EEE) To Reduce Power Consumption In Transceivers In LPI State • Full-Chip Hardware or Software Power Down (All Registers Value are not Saved and Strap-In Value will Re-Strap after Releasing the Power Down) • Energy Detect Power Down (EDPD), which Disables the PHY Transceiver when Cables are Removed • Wake On LAN Supported with Configurable Packet Control • Dynamic Clock Tree Control to Reduce Clocking in Areas not in Use • Power Consumption Less than 0.5W
Additional Features
• Single 25 MHz +50 ppm Reference Clock Requirement • Comprehensive Programmable Two LED Indica- tors Support for Link, Activity, Full/Half Duplex and 10/100 Speed
Packaging
• Commercial Temperature Range: 0°C to +70°C and Extended Industrial Temperature Ranges: –40°C to +105°C and –40°C to +115°C • 64-pin (10 mm × 10 mm) Lead Free (RoHS) LQFP Package with Heat Exposed Ground Paddle for Low Thermal Resistance • 0.11 µm Technology for Lower Power Consumption DS00002761A-page 2 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 MDI/MDI−X Auto Crossover 3.4 Auto Negotiation 3.5 LINK MD® Cable Diagnostics 3.6 On-Chip Termination Resistors 3.7 Lookback Support 3.8 MAC (Media Access Controller) Block 3.9 Switch Block 3.10 IGMP Support 3.11 IPv6 MLD Snooping 3.12 Port Mirroring Support 3.13 IEEE 802.1Q VLAN Support 3.14 QoS Priority Support 3.15 Rate-Limiting Support 3.16 MAC Address Filtering Function 3.17 Queue Management Unit (QMU) 3.18 Device Clocks 3.19 Power 3.20 Internal Low Voltage LDO Regulator 3.21 Power Management 3.22 Wake-On-LAN 3.23 Interfaces 4.0 Register Descriptions 4.1 Device Registers 4.2 Register Map of CPU Accessible I/O Registers 4.3 Register Bit Definitions 4.4 Type-of-Service (TOS) Priority Control Registers 4.5 Indirect Access Data Registers 4.6 Power Management Control and Wake-Up Event Status 4.7 Go Sleep Time and Clock Tree Power-Down Control Registers 4.8 PHY and MII Basic Control Registers 4.9 Port 1 Control Registers 4.10 Port 2 Control Registers 4.11 Port 3 Control Registers 4.12 Switch Global Control Registers 4.13 Source Address Filtering Registers 4.14 TXQ Rate Control Registers 4.15 Auto-Negotiation Next Page Registers 4.16 EEE and Link Partner Advertisement Registers 4.17 Internal I/O Register Space Mapping for Interrupts, BIU, and Global Reset (0x100 - 0x1FF) 4.18 Host MAC Address Registers: MARL, MARM, and MARH 4.19 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x170 - 0x1FF) 4.20 Internal I/O Register Space Mapping for Interrupt Registers (0x190 - 0x193) 4.21 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x19C - 0x1B9) 4.22 Management Information Base (MIB) Counters 4.23 Static MAC Address Table 4.24 Dynamic MAC Address Table 4.25 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read / Write Timing 7.2 Auto-Negotiation Timing 7.3 Serial EEPROM Interface Timing 7.4 Reset Timing and Power Sequencing 7.5 Reset Circuit Guidelines 7.6 Reference Circuits – LED Strap-In Pins 7.7 Reference Clock – Connection and Selection 8.0 Selection of Isolation Transformers 9.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
Marks for Flow Control in RX FIFO
Applications
• Efficient Architecture Design with Configurable Host Interrupt Schemes to Minimize Host CPU • General and Industrial Ethernet Applications Overhead and Utilization • Wireless LAN Access Point and Gateway • Queue Management Unit (QMU) Supervises Data • Set Top / Game Box Transfers Across this Interface • Test and Measurement Equipment
Power and Power Management
• Automotive • Single 3.3V Power Supply with Optional VDD I/O for 1.8V, 2.5V, or 3.3V • Integrated Low-Voltage (~1.3V) Low-Noise Regulator (LDO) Output for Digital and Analog Core Power • Supports IEEE P802.3az™ Energy Efficient Ethernet (EEE) To Reduce Power Consumption In Transceivers In LPI State • Full-Chip Hardware or Software Power Down (All Registers Value are not Saved and Strap-In Value will Re-Strap after Releasing the Power Down) • Energy Detect Power Down (EDPD), which Disables the PHY Transceiver when Cables are Removed • Wake On LAN Supported with Configurable Packet Control • Dynamic Clock Tree Control to Reduce Clocking in Areas not in Use • Power Consumption Less than 0.5W
Additional Features
• Single 25 MHz +50 ppm Reference Clock Requirement • Comprehensive Programmable Two LED Indica- tors Support for Link, Activity, Full/Half Duplex and 10/100 Speed
Packaging
• Commercial Temperature Range: 0°C to +70°C and Extended Industrial Temperature Ranges: –40°C to +105°C and –40°C to +115°C • 64-pin (10 mm × 10 mm) Lead Free (RoHS) LQFP Package with Heat Exposed Ground Paddle for Low Thermal Resistance • 0.11 µm Technology for Lower Power Consumption DS00002761A-page 2 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 MDI/MDI−X Auto Crossover 3.4 Auto Negotiation 3.5 LINK MD® Cable Diagnostics 3.6 On-Chip Termination Resistors 3.7 Lookback Support 3.8 MAC (Media Access Controller) Block 3.9 Switch Block 3.10 IGMP Support 3.11 IPv6 MLD Snooping 3.12 Port Mirroring Support 3.13 IEEE 802.1Q VLAN Support 3.14 QoS Priority Support 3.15 Rate-Limiting Support 3.16 MAC Address Filtering Function 3.17 Queue Management Unit (QMU) 3.18 Device Clocks 3.19 Power 3.20 Internal Low Voltage LDO Regulator 3.21 Power Management 3.22 Wake-On-LAN 3.23 Interfaces 4.0 Register Descriptions 4.1 Device Registers 4.2 Register Map of CPU Accessible I/O Registers 4.3 Register Bit Definitions 4.4 Type-of-Service (TOS) Priority Control Registers 4.5 Indirect Access Data Registers 4.6 Power Management Control and Wake-Up Event Status 4.7 Go Sleep Time and Clock Tree Power-Down Control Registers 4.8 PHY and MII Basic Control Registers 4.9 Port 1 Control Registers 4.10 Port 2 Control Registers 4.11 Port 3 Control Registers 4.12 Switch Global Control Registers 4.13 Source Address Filtering Registers 4.14 TXQ Rate Control Registers 4.15 Auto-Negotiation Next Page Registers 4.16 EEE and Link Partner Advertisement Registers 4.17 Internal I/O Register Space Mapping for Interrupts, BIU, and Global Reset (0x100 - 0x1FF) 4.18 Host MAC Address Registers: MARL, MARM, and MARH 4.19 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x170 - 0x1FF) 4.20 Internal I/O Register Space Mapping for Interrupt Registers (0x190 - 0x193) 4.21 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x19C - 0x1B9) 4.22 Management Information Base (MIB) Counters 4.23 Static MAC Address Table 4.24 Dynamic MAC Address Table 4.25 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read / Write Timing 7.2 Auto-Negotiation Timing 7.3 Serial EEPROM Interface Timing 7.4 Reset Timing and Power Sequencing 7.5 Reset Circuit Guidelines 7.6 Reference Circuits – LED Strap-In Pins 7.7 Reference Clock – Connection and Selection 8.0 Selection of Isolation Transformers 9.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service