Datasheet ADAR1000 (Analog Devices) - 10

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ADAR1000 Data Sheet Table 5. Pin Function Descriptions Pin No. Mnemonic Description
A1 DET3 Channel 3 Power Detector Input. DET3 is internally ac-coupled and enabled by Register 0x030, Bit 1. The nominal operating input power range is −20 dBm to +10 dBm. A2, A6, A8, A12, A13, B1, GND RF Ground. Tie all ground pins together to a low impedance plane on the PCB board. B2, B6 to B10, B12, B13, C2, C12, D1, D2, D12, D13, E2, E12, F1, F2, F12, F13, G2, G12, H1, H2, H12, H13, J2, J12, K1, K2, K12, K13, L2, L12, M1, M2, M7, M12, M13, N1, N7, N8, N12 A3 TR_SW_NEG Gate Control Output for External Transmit and Receive Switch (0 V or −5 V). A4 PA_BIAS4 Gate Bias Output for Channel 4 External PA. Output ranges from 0 to −4.8 V, controlled by a combination of the PA_ON pin, Register 0x02C (CH4_PA_BIAS_ON value), and Register 0x049 (CH4_PA_BIAS_OFF value). Output is set to the CH4_PA_BIAS_OFF value if the PA_ON pin is at logic low. A5 PA_BIAS3 Gate Bias Output for Channel 3 External PA. Output ranges from 0 to −4.8 V, controlled by a combination of the PA_ON pin, Register 0x02B (CH3_PA_BIAS_ON value), and Register 0x048 (CH3_PA_BIAS_OFF value). Output is set to the CH3_PA_BIAS_OFF value if the PA_ON pin is at logic low. A7 RF_IO Common RF Pin for Input in Transmit Mode and Output in Receive Mode. A9 PA_BIAS2 Gate Bias Output for Channel 2 External PA. Output ranges from 0 to −4.8 V, controlled by a combination of the PA_ON pin, Register 0x02A (CH2_PA_BIAS_ON value), and Register 0x047 (CH2_PA_BIAS_OFF value). Output is set to the CH2_PA_BIAS_OFF value if the PA_ON pin is at logic low. A10 PA_BIAS1 Gate Bias Output for Channel 1 External PA. Output ranges from 0 to −4.8 V, controlled by a combination of the PA_ON pin, Register 0x029 (CH1_PA_BIAS_ON value), and Register 0x046 (CH1_PA_BIAS_OFF value). Output is set to the CH1_PA_BIAS_OFF value if the PA_ON pin is at logic low. A11 LNA_BIAS Gate Bias Output for External LNA. Output ranges from 0 to −4.8 V, controlled by a combination of Register 0x030 (Bit 4, LNA_BIAS_OUT_EN), Register 0x02D (LNA_BIAS_ON value), and Register 0x04A (LNA_BIAS_OFF value). Output floats if Register 0x030, Bit 4 is at logic low. B3 PA_ON PA Enable Input. Set this pin to logic high for PA bias voltages to assume the values set by the EXT_PAx_BIAS_ON and EXT_PAx_BIAS_OFF registers (x = 1 to 4). All PA_BIASx outputs take on the corresponding CHx_PA_BIAS_OFF value if the PA_ON pin is at logic low. This pin is internally pulled up to the 1.8 V low dropout (LDO) regulator bias voltage with a 100 kΩ resistor. B4 TR_POL Gate Control Output for External Polarization Switch (0 V or −5 V). B5 TR_SW_POS Gate Control Positive Output for External Transmit and Receive Switch (0 V or 3.3 V). B11 AVDD1 −5 V Power Supply. AVDD1 provides the negative currents for sinking the PA_BIASx and LNA_BIAS outputs. If the PA_BIASx and LNA_BIAS pins are not used, the user can connect AVDD1 to ground to reduce power consumption and to use a single voltage supply. C1 TX3 Channel 3 Output in Transmit Mode. C13 RX2 Channel 2 Input in Receive Mode. E1 RX3 Channel 3 Input in Receive Mode. E13 TX2 Channel 2 Output in Transmit Mode. G1 DET4 Channel 4 Power Detector Input. DET4 is internally ac-coupled and enabled by Register 0x030, Bit 0. The nominal operating input power range is −20 dBm to +10 dBm. G13 DET2 Channel 2 Power Detector Input. DET2 is internally ac-coupled and enabled by Register 0x030, Bit 2. The nominal operating input power range is −20 dBm to +10 dBm. J1 TX4 Channel 4 Output in Transmit Mode. J13 RX1 Channel 1 Input in Receive Mode. L1 RX4 Channel 4 Input in Receive Mode. L13 TX1 Channel 1 Output in Transmit Mode. M3 CSB SPI Chip Select Input (1.8 V CMOS Logic). Serial communication is enabled when CSB goes low. When CSB goes high, serial data is loaded into the register corresponding to the address in the instruction cycle (see Figure 2) in write mode. Rev. A | Page 10 of 65 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams SPI Block Write Mode SPI Write All Mode Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Path Phase and Gain Control Power Detectors External Amplifier Bias DACs External Switch Control Transmit and Receive Control RF Subcircuit Bias Control and Enables ADC Operation Chip Addressing Memory Access Calibration Applications Information Gain Control Registers Switched Attenuator Control Phase Control Registers Transmit and Receive Subcircuit Control TR_SOURCE = 1 (TR Pin Control) TR_SOURCE = 0 (SPI Control) Transmit and Receive Switch Driver Control PA Bias Output Control LNA Bias Output Control Transmit/Receive Delay Control Transmit and Receive Mode Switching SPI Programming Example Powering the ADAR1000 Register Map Register Descriptions Outline Dimensions Ordering Guide