Datasheet ADAR1000 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | 8 GHz to 16 GHz, 4-Channel, X Band and Ku Band Beamformer |
| Páginas / Página | 65 / 2 — ADAR1000. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 3/2019—Rev. 0 … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 1.7 Mb |
| Idioma del documento | Inglés |
ADAR1000. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 3/2019—Rev. 0 to Rev. A. 6/2018—Revision 0: Initial Version
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ADAR1000 Data Sheet TABLE OF CONTENTS
Features .. 1 ADC Operation .. 26 Applications ... 1 Chip Addressing ... 27 General Description ... 1 Memory Access ... 27 Functional Block Diagram .. 1 Calibration... 27 Revision History ... 2 Applications Information .. 33 Specifications ... 3 Gain Control Registers .. 33 Timing Specifications .. 6 Switched Attenuator Control .. 33 Absolute Maximum Ratings .. 8 Phase Control Registers ... 34 Thermal Resistance .. 8 Transmit and Receive Subcircuit Control ... 36 ESD Caution .. 8 Transmit and Receive Switch Driver Control ... 36 Pin Configuration and Function Descriptions ... 9 PA Bias Output Control ... 37 Typical Performance Characteristics ... 12 LNA Bias Output Control ... 37 Theory of Operation .. 24 Transmit/Receive Delay Control .. 37 RF Path ... 24 SPI Programming Example ... 39 Phase and Gain Control .. 24 Powering the ADAR1000 .. 41 Power Detectors .. 25 Register Map ... 42 External Amplifier Bias DACs .. 25 Register Descriptions ... 44 External Switch Control .. 25 Outline Dimensions ... 65 Transmit and Receive Control .. 26 Ordering Guide .. 65 RF Subcircuit Bias Control and Enables.. 26
REVISION HISTORY 3/2019—Rev. 0 to Rev. A
Added Figure 86 ... 24 Change to Phase and Gain Switching Time Parameter, Table 1 .. 5 Changes to External Switch Control Section .. 25 Added SPI Write Al Mode Section and Figure 6; Renumbered Changes to Table 6 .. 26 Sequentially ... 7 Added Chip Addressing Section .. 27 Added Figure 8 .. 9 Changes to Memory Access Section .. 27 Changes to Table 5 .. 10 Added Table 7, Table 8, and Table 9, and Table 10; Renumbered Reorganized Typical Performance Characteristics Section Sequentially .. 27 Layout ... 12 Added Phase Control Registers Section, Table 13, and Changes to Figure 12 .. 12 Table 14 .. 34 Added Figure 21 .. 14 Added Table 15 and Table 16 .. 35 Changes to Figure 26 .. 14 Added Transmit/Receive Delay Control Section ... 37 Changes to Figure 31 .. 15 Changes to Figure 92 .. 38 Changes to Figure 33 .. 16 Changes to Table 20 ... 39 Added Figure 40 .. 17 Added Table 21 ... 40 Added Figure 46 and Figure 49... 18 Added Powering the ADAR1000 Section, Figure 93 to Figure 97, Changes to Figure 50 and Caption ... 18 and Table 22 .. 41 Changes to Figure 54, Figure 55, and Figure 56 ... 19 Changes to Figure 60 and Figure 61 ... 20
6/2018—Revision 0: Initial Version
Changes to Phase and Gain Control Section .. 24 Rev. A | Page 2 of 65 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams SPI Block Write Mode SPI Write All Mode Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Path Phase and Gain Control Power Detectors External Amplifier Bias DACs External Switch Control Transmit and Receive Control RF Subcircuit Bias Control and Enables ADC Operation Chip Addressing Memory Access Calibration Applications Information Gain Control Registers Switched Attenuator Control Phase Control Registers Transmit and Receive Subcircuit Control TR_SOURCE = 1 (TR Pin Control) TR_SOURCE = 0 (SPI Control) Transmit and Receive Switch Driver Control PA Bias Output Control LNA Bias Output Control Transmit/Receive Delay Control Transmit and Receive Mode Switching SPI Programming Example Powering the ADAR1000 Register Map Register Descriptions Outline Dimensions Ordering Guide
ADAR1000 Data Sheet TABLE OF CONTENTS
Features .. 1 ADC Operation .. 26 Applications ... 1 Chip Addressing ... 27 General Description ... 1 Memory Access ... 27 Functional Block Diagram .. 1 Calibration... 27 Revision History ... 2 Applications Information .. 33 Specifications ... 3 Gain Control Registers .. 33 Timing Specifications .. 6 Switched Attenuator Control .. 33 Absolute Maximum Ratings .. 8 Phase Control Registers ... 34 Thermal Resistance .. 8 Transmit and Receive Subcircuit Control ... 36 ESD Caution .. 8 Transmit and Receive Switch Driver Control ... 36 Pin Configuration and Function Descriptions ... 9 PA Bias Output Control ... 37 Typical Performance Characteristics ... 12 LNA Bias Output Control ... 37 Theory of Operation .. 24 Transmit/Receive Delay Control .. 37 RF Path ... 24 SPI Programming Example ... 39 Phase and Gain Control .. 24 Powering the ADAR1000 .. 41 Power Detectors .. 25 Register Map ... 42 External Amplifier Bias DACs .. 25 Register Descriptions ... 44 External Switch Control .. 25 Outline Dimensions ... 65 Transmit and Receive Control .. 26 Ordering Guide .. 65 RF Subcircuit Bias Control and Enables.. 26
REVISION HISTORY 3/2019—Rev. 0 to Rev. A
Added Figure 86 ... 24 Change to Phase and Gain Switching Time Parameter, Table 1 .. 5 Changes to External Switch Control Section .. 25 Added SPI Write Al Mode Section and Figure 6; Renumbered Changes to Table 6 .. 26 Sequentially ... 7 Added Chip Addressing Section .. 27 Added Figure 8 .. 9 Changes to Memory Access Section .. 27 Changes to Table 5 .. 10 Added Table 7, Table 8, and Table 9, and Table 10; Renumbered Reorganized Typical Performance Characteristics Section Sequentially .. 27 Layout ... 12 Added Phase Control Registers Section, Table 13, and Changes to Figure 12 .. 12 Table 14 .. 34 Added Figure 21 .. 14 Added Table 15 and Table 16 .. 35 Changes to Figure 26 .. 14 Added Transmit/Receive Delay Control Section ... 37 Changes to Figure 31 .. 15 Changes to Figure 92 .. 38 Changes to Figure 33 .. 16 Changes to Table 20 ... 39 Added Figure 40 .. 17 Added Table 21 ... 40 Added Figure 46 and Figure 49... 18 Added Powering the ADAR1000 Section, Figure 93 to Figure 97, Changes to Figure 50 and Caption ... 18 and Table 22 .. 41 Changes to Figure 54, Figure 55, and Figure 56 ... 19 Changes to Figure 60 and Figure 61 ... 20
6/2018—Revision 0: Initial Version
Changes to Phase and Gain Control Section .. 24 Rev. A | Page 2 of 65 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams SPI Block Write Mode SPI Write All Mode Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Path Phase and Gain Control Power Detectors External Amplifier Bias DACs External Switch Control Transmit and Receive Control RF Subcircuit Bias Control and Enables ADC Operation Chip Addressing Memory Access Calibration Applications Information Gain Control Registers Switched Attenuator Control Phase Control Registers Transmit and Receive Subcircuit Control TR_SOURCE = 1 (TR Pin Control) TR_SOURCE = 0 (SPI Control) Transmit and Receive Switch Driver Control PA Bias Output Control LNA Bias Output Control Transmit/Receive Delay Control Transmit and Receive Mode Switching SPI Programming Example Powering the ADAR1000 Register Map Register Descriptions Outline Dimensions Ordering Guide