Datasheet ADAR1000 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 8 GHz to 16 GHz, 4-Channel, X Band and Ku Band Beamformer |
| Páginas / Página | 65 / 9 — Data Sheet. ADAR1000. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. 1 2 3 … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 1.7 Mb |
| Idioma del documento | Inglés |
Data Sheet. ADAR1000. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. 1 2 3 4 5 6 7 8 9 10111213. A B C D. TOP VIEW. (Not to Scale)
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Data Sheet ADAR1000 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10111213 A B C D E F ADAR1000 G TOP VIEW H (Not to Scale) J K L M N NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD AND
006
ALL GND CONNECTIONS TO A LOW IMPEDANCE GROUND PLANE ON THE PCB.
16790- Figure 7. Pin Configuration (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 A DET3 GND TR_SW_NEG PA_BIAS4 PA_BIAS3 GND RF_IO GND PA_BIAS2 PA_BIAS1 LNA_BIAS GND GND B GND GND PA_ON TR_POL TR_SW_POS GND GND GND GND GND AVDD1 GND GND C TX3 GND GND RX2 NO PINS D GND GND GND GND E RX3 GND GND TX2 F GND GND GND GND EXPOSED PAD CONNECT TO LOW IMPEDANCE GROUND PLANE ON PCB G DET4 GND GND DET2 H GND GND GND GND J TX4 GND GND RX1 K GND GND GND GND L RX4 GND NO PINS GND TX1 M GND GND CSB SDO SDIO SCLK GND CREG1 CREG2 AVDD3 AVDD3 GND GND N GND RX_LOAD TX_LOAD ADDR0 ADDR1 TR GND GND CREG4 CREG3 AVDD3 GND DET1 GROUND RF INPUT/OUTPUT BEAM CONTROL SPI 3.3V ANALOG SUPPLY EXT BIAS OUTPUT REGULATOR DECOUPLING CHIP ADDRESS
108
–5V ANALOG SUPPLY DETECTOR OUTPUT PA BIAS CONTROL EXPOSED PAD
16790- Figure 8. Pin Configuration, Color Coded (Top View) Rev. A | Page 9 of 65 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams SPI Block Write Mode SPI Write All Mode Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Path Phase and Gain Control Power Detectors External Amplifier Bias DACs External Switch Control Transmit and Receive Control RF Subcircuit Bias Control and Enables ADC Operation Chip Addressing Memory Access Calibration Applications Information Gain Control Registers Switched Attenuator Control Phase Control Registers Transmit and Receive Subcircuit Control TR_SOURCE = 1 (TR Pin Control) TR_SOURCE = 0 (SPI Control) Transmit and Receive Switch Driver Control PA Bias Output Control LNA Bias Output Control Transmit/Receive Delay Control Transmit and Receive Mode Switching SPI Programming Example Powering the ADAR1000 Register Map Register Descriptions Outline Dimensions Ordering Guide
006
ALL GND CONNECTIONS TO A LOW IMPEDANCE GROUND PLANE ON THE PCB.
16790- Figure 7. Pin Configuration (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 A DET3 GND TR_SW_NEG PA_BIAS4 PA_BIAS3 GND RF_IO GND PA_BIAS2 PA_BIAS1 LNA_BIAS GND GND B GND GND PA_ON TR_POL TR_SW_POS GND GND GND GND GND AVDD1 GND GND C TX3 GND GND RX2 NO PINS D GND GND GND GND E RX3 GND GND TX2 F GND GND GND GND EXPOSED PAD CONNECT TO LOW IMPEDANCE GROUND PLANE ON PCB G DET4 GND GND DET2 H GND GND GND GND J TX4 GND GND RX1 K GND GND GND GND L RX4 GND NO PINS GND TX1 M GND GND CSB SDO SDIO SCLK GND CREG1 CREG2 AVDD3 AVDD3 GND GND N GND RX_LOAD TX_LOAD ADDR0 ADDR1 TR GND GND CREG4 CREG3 AVDD3 GND DET1 GROUND RF INPUT/OUTPUT BEAM CONTROL SPI 3.3V ANALOG SUPPLY EXT BIAS OUTPUT REGULATOR DECOUPLING CHIP ADDRESS
108
–5V ANALOG SUPPLY DETECTOR OUTPUT PA BIAS CONTROL EXPOSED PAD
16790- Figure 8. Pin Configuration, Color Coded (Top View) Rev. A | Page 9 of 65 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams SPI Block Write Mode SPI Write All Mode Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Path Phase and Gain Control Power Detectors External Amplifier Bias DACs External Switch Control Transmit and Receive Control RF Subcircuit Bias Control and Enables ADC Operation Chip Addressing Memory Access Calibration Applications Information Gain Control Registers Switched Attenuator Control Phase Control Registers Transmit and Receive Subcircuit Control TR_SOURCE = 1 (TR Pin Control) TR_SOURCE = 0 (SPI Control) Transmit and Receive Switch Driver Control PA Bias Output Control LNA Bias Output Control Transmit/Receive Delay Control Transmit and Receive Mode Switching SPI Programming Example Powering the ADAR1000 Register Map Register Descriptions Outline Dimensions Ordering Guide