Datasheet ADAR1000 (Analog Devices) - 6

ADAR1000 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS TR, RX_LOAD, TX_LOAD, CSB, SCLK, and SDIO pins Input High Voltage (VIH) 1.0 V Input Low Voltage (VIL) 0.3 V High and Low Input Current, (IINH, IINL) ±1 μA Input Capacitance (CIN) 1 pF LOGIC OUTPUTS SDO and SDIO pins Output High Voltage, (VOH) Output high current (IOH) = −10 mA 1.4 V Output Low Voltage, (VOL) Output low current (IOL) = 10 mA 0.4 V POWER SUPPLIES AVDD1 −5.25 −5 −4.75 V AVDD3 3.1 3.3 3.5 V IAVDD1 Quiescent (reset state) −4 mA IAVDD1 PA bias outputs fully loaded −50 mA IAVDD3 Reset Mode (Standby) 23 mA Transmit Mode Four channels enabled, nominal bias 350 mA Four channels enabled, low bias 240 mA setting Receive Mode Four channels enabled, nominal bias 260 mA Four channels enabled, low bias 160 mA setting 1 From one transmit channel port to another, both channels must be set to the maximum gain. 2 Measured gain is the ratio of the output power at RF_IO to the input power applied to any single receive port, with the other three receive ports terminated in 50 Ω. 3 Channel gain is the ratio of the output power at RF_IO to the input power applied to any single receive port, with the other three receive ports driven and phased for coherent combining, excluding the 6 dB combining gain. The channel gain is approximately 6 dB higher than the measured gain. 4 From one receive channel port to another, both channels must be set to the maximum gain.
TIMING SPECIFICATIONS
AVDD1 = −5 V, AVDD3 = +3.3 V, TA = 25°C, unless otherwise noted.
Table 2. SPI Timing Parameter Min Typ Max Unit Test Conditions/Comments
Maximum Clock Rate (tSCLK) 25 MHz Minimum Pulse Width High (tPWH) 10 ns Minimum Pulse Width Low (tPWL) 10 ns Setup Time, SDIO to SCLK (tDS) 5 ns Hold Time, SDIO to SCLK (tDH) 5 ns Data Valid, SDO to SCLK (tDV) 5 ns Setup Time, CSB to SCLK (tDCS) 10 ns SDIO, SDO Rise Time (tR) 20 ns Outputs loaded with 80 pF, 10% to 90% SDIO, SDO Fall Time (tF) 20 ns Outputs loaded with 80 pF, 10% to 90%
Timing Diagrams CSB INSTRUCTION CYCLE DATA TRANSFER CYCLE SCLK
2 -00
SDIO R/W A14 A13 A3 A2 A1 A0 D7
90
N D6N D5N D30 D20 D10 D00
167 Figure 2. Serial Port Interface Register Timing (MSB First) Rev. A | Page 6 of 65 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams SPI Block Write Mode SPI Write All Mode Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Path Phase and Gain Control Power Detectors External Amplifier Bias DACs External Switch Control Transmit and Receive Control RF Subcircuit Bias Control and Enables ADC Operation Chip Addressing Memory Access Calibration Applications Information Gain Control Registers Switched Attenuator Control Phase Control Registers Transmit and Receive Subcircuit Control TR_SOURCE = 1 (TR Pin Control) TR_SOURCE = 0 (SPI Control) Transmit and Receive Switch Driver Control PA Bias Output Control LNA Bias Output Control Transmit/Receive Delay Control Transmit and Receive Mode Switching SPI Programming Example Powering the ADAR1000 Register Map Register Descriptions Outline Dimensions Ordering Guide