Datasheet ACG1F (Cypress) - 5

PRELIMINARY ACG1F Power System Overview
ACG1F operates on a single power-supply input VDDD with a valid range of (2.7 V–5.5 V). In addition, there is a V5V supply pin that sources the VCONN supply to the Type-C connector; the valid levels on the V5V supply can range from 4.85 V–5.5 V. V5V does not power the chip. The V5V supply support operation over 4.85 V–5.5 V while the VDDD input supports operation over 2.7 V–5.5 V. ACG1F has two different power modes: Active and Deep Sleep, transitions between which are managed by the Power System. A separate power domain VDDIO is provided for the GPIOs. VDDD should be shorted to VDDIO at system level. The VCCD pin, the output of the core (1.8 V) regulator, is brought out for connecting a 0.1-µF capacitor for the regulator stability only. The VCCD pin is not supported as a power supply.
Figure 1. ACG1F Power System
VDDD VBUS_P NGDO 1uF VBUS_C CC1 CC2 V5V Core Regulator (SRSS-Lite) VCCD VDDIO TYPE-C 0.1 uF GPIOs Core PHY VSS
Power Modes
The power modes of the device, accessible and observable by the user, are listed in the following table.
Table 1. ACG1F Power Modes Mode Description
RESET Power is valid and XRES is not asserted. An internal reset source is asserted or SleepController is sequencing the system out of reset. ACTIVE Power is valid and CPU is executing instructions. DEEP SLEEP Main regulator and most hard-IPs are shut down. DeepSleep regulator powers logic, but only low-frequency clock is available. SCAN System is in Scan mode. Scan mode is entered by applying DFT key during XRES and exited by applying something other than the DFT key (at least one bit). Document Number: 002-26356 Rev. *C Page 5 of 27 Document Outline General Description Features USB Type-C Support Integrated VBUS Load Switch Controller 2x I2C Legacy Charging 32-bit MCU Subsystem Packages Application Diagram Contents Functional Overview USB-C Subsystem USB-PD Physical Layer VCONN FET ADC Undervoltage and Overvoltage Protection on VBUS High-side Current Sense Amplifier for VBUS VBUS Reverse Current Protection VBUS Discharge VBUS Load Switch Gate Driver for VBUS NFET Charger Detect MCU and Memory CPU Flash SROM SRAM Power System Overview Power Modes Peripherals Timer/Counter/PWM Block (TCPWM) GPIO Pinouts Electrical Specifications Absolute Maximum Ratings Device-Level Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter Charger Detect CSA VBUS UV/OV VCONN Switch VBUS Provider NFET RCP Ordering Information Ordering Code Definition Packaging Acronyms Document Conventions Units of Measure Errata Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support