Datasheet ACG1F (Cypress) - 6

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PRELIMINARY ACG1F Peripherals Timer/Counter/PWM Block (TCPWM)
ACG1F has two SCBs, which can each implement only an I2C. The timer block of ACG1F supports one timer or counter or
I2C Mode:
The hardware I2C block implements a full pulse-width modulator. The timer is available for internal timer multi-master and slave interface (it is capable of multimaster use by firmware or for providing PWM-based functions on the arbitration). This block is capable of operating at speeds of up to GPIOs. 1 Mbps (Fast Mode Plus) and has flexible buffering options to
GPIO
reduce interrupt overhead and latency for the CPU. The ACG1F die has 8 GPIOs in 40-QFN and 5 GPIOs in 24-QFN The SCB blocks support 8-deep FIFOs for Receive and including the I2C and SWD pins, which can also be used as Transmit, which, by increasing the time given for the CPU to read GPIOs. The GPIO block shall implement the following: data, greatly reduces the need for clock stretching caused by the CPU not having read data on time. The FIFO mode is available ■ Eight drive strength modes including strong push-pull, resistive in all channels and is very useful in the absence of DMA. Data pull-up and pull-down, weak (resistive) pull-up and pull-down, throughput is not a critical consideration for I2C. open drain and open source, input only, and disabled. The I2C peripheral is compatible with the I2C Standard-mode, ■ Input threshold select (CMOS or LVTTL) Fast-mode, and Fast-Mode Plus devices as defined in the NXP I2C bus specification and user manual (UM10204). The I2C bus ■ Individual control of input and output disables. I/O is implemented with GPIO in open-drain modes. The I2C bus ■ Hold mode for latching previous state (used for retaining I/O uses open-drain drivers for clock and data with pull-up resistors state in Deep Sleep mode). on the bus for clock and data connected to all nodes. The required Rise and Fall times for different I2C speeds are ■ Selectable slew rates for dV/dt related noise control. guaranteed by using appropriate pull-up resistor values During power-on and reset, the blocks are forced to the Disable depending on VDDD, bus capacitance, and resistor tolerance. state so as not to crowbar any inputs and/or cause excess For detailed information on how to calculate the optimum pull-up turn-on current. A multiplexing network known as a high-speed resistor value for your design, refer to the UM10204 I2C bus I/O matrix is used to multiplex between various signals that may specification and user manual (the latest revision is available at connect to an I/O pin. Pin locations for fixed-function peripherals, www.nxp.com). such as the USB Type-C port, are also fixed in order to reduce One of the SCB (typically SCB1) blocks is used to implement the internal multiplexing complexity. Data Output Registers and Pin Host Processor Interface (HPI) slave, which allows an external State Registers store, respectively, the values to be driven on the MCU to control the firmware operation. pins and the states of the pins themselves. The pins can be The HPI I2C slave address is configurable using the configured by programming of registers through software for each digital I/O Port. I2C_CFG_EC pin for ACG1F 40-QFN as shown in Table 2. The default address for ACG1F 24-QFN will be 0x66. Every I/O pin can generate an interrupt if so enabled and each I/O Port has an Interrupt Request (IRQ) and Interrupt Service
Table 2. I2C Slave Address Configuration
Routine (ISR) Vector associated with it. The I/O ports can retain their state during Deep Sleep mode or
I2C_CFG_EC Configuration I2C Slave
remain ON. If the operation is restored using reset, then the pins Floating 0x60 shall go the High-Z state. If operation is restored by an interrupt event, then the pin drivers shall retain their state until firmware Pulled up with 1 k 0x64 chooses to change it. The I/Os (on data bus) do not draw current Pulled down with 1 k 0x62 on power down. Document Number: 002-26356 Rev. *C Page 6 of 27 Document Outline General Description Features USB Type-C Support Integrated VBUS Load Switch Controller 2x I2C Legacy Charging 32-bit MCU Subsystem Packages Application Diagram Contents Functional Overview USB-C Subsystem USB-PD Physical Layer VCONN FET ADC Undervoltage and Overvoltage Protection on VBUS High-side Current Sense Amplifier for VBUS VBUS Reverse Current Protection VBUS Discharge VBUS Load Switch Gate Driver for VBUS NFET Charger Detect MCU and Memory CPU Flash SROM SRAM Power System Overview Power Modes Peripherals Timer/Counter/PWM Block (TCPWM) GPIO Pinouts Electrical Specifications Absolute Maximum Ratings Device-Level Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter Charger Detect CSA VBUS UV/OV VCONN Switch VBUS Provider NFET RCP Ordering Information Ordering Code Definition Packaging Acronyms Document Conventions Units of Measure Errata Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support