Datasheet AD9279 (Analog Devices) - 3

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AD9279 SPECIFICATIONS AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (−40°C to +85°C), fIN = 5 MHz, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.3 dB, LNA bias = default, PGA gain = 27 dB, GAIN− = 0.8 V, GAIN+ = 0 V, AAF LPF cutoff = fSAMPLE/3 (MODE I/II) = fSAMPLE/4.5 (MODE III), HPF cutoff = LPF cutoff/12, MODE I = fSAMPLE = 40 MSPS, MODE II = fSAMPLE = 65 MSPS, MODE III = fSAMPLE = 80 MSPS, low power LVDS mode, unless otherwise noted.
Table 1. Parameter1 Test Conditions/Comments Min Typ Max Unit
LNA CHARACTERISTICS Gain Single-ended input to differential 15.6/17.9/21.3 dB output Single-ended input to single-ended 9.6/11.9/15.3 dB output 0.1 dB Input Compression Point LNA gain = 15.6 dB 1.00 V p-p LNA gain = 17.9 dB 0.75 V p-p LNA gain = 21.3 dB 0.45 V p-p 1 dB Input Compression Point LNA gain = 15.6 dB 1.20 V p-p LNA gain = 17.9 dB 0.90 V p-p LNA gain = 21.3 dB 0.60 V p-p Input Common Mode (LI-x, LG-x) 2.2 V Output Common Mode (LO-x) Switch off High-Z Ω Switch on 1.5 V Output Common Mode (LOSW-x) Switch off High-Z Ω Switch on 1.5 V Input Resistance (LI-x) RFB = 350 Ω, LNA gain = 21.3 dB 50 Ω RFB = 1400 Ω, LNA gain = 21.3 dB 200 Ω RFB = ∞, LNA gain = 21.3 dB 6 kΩ Input Capacitance (LI-x) 22 pF −3 dB Bandwidth LNA gain = 15.6 dB 150 MHz LNA gain = 17.9 dB 130 MHz LNA gain = 21.3 dB 100 MHz Input Noise Voltage RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB 0.95 nV/√Hz LNA gain = 17.9 dB 0.85 nV/√Hz LNA gain = 21.3 dB 0.75 nV/√Hz Input Noise Current RFB = ∞ 2.5 pA/√Hz Noise Figure RS = 50 Ω Active Termination Matched LNA gain = 15.6 dB, RFB = 200 Ω 4.5 dB LNA gain = 17.9 dB, RFB = 250 Ω 3.7 dB LNA gain = 21.3 dB, RFB = 350 Ω 2.9 dB Unterminated LNA gain = 15.6 dB, RFB = ∞ 3.1 dB LNA gain = 17.9 dB, RFB = ∞ 2.6 dB LNA gain = 21.3 dB, RFB = ∞ 2.2 dB FULL-CHANNEL (TGC) CHARACTERISTICS AAF Low-Pass Cutoff −3 dB, programmable 8 18 MHz In Range AAF Bandwidth ±10 % Tolerance Group Delay Variation f = 1 MHz to 18 MHz, GAIN+ = 0 V to 1.6 V ±0.3 ns Rev. 0 | Page 3 of 44 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS ULTRASOUND THEORY OF OPERATION CHANNEL OVERVIEW TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise Input Overdrive Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Recommendations Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE