Datasheet AD9279 (Analog Devices) - 10

AD9279 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 A LI-E LI-F LI-G LI-H VREF RBIAS GAIN+ GAIN– LI-A LI-B LI-C LI-D B LG-E LG-F LG-G LG-H GND GND AVDD2 GND LG-A LG-B LG-C LG-D C LO-E LO-F LO-G LO-H GND GND GND GND LO-A LO-B LO-C LO-D D LOSW-E LOSW-F LOSW-G LOSW-H GND GND GND GND LOSW-A LOSW-B LOSW-C LOSW-D E GND AVDD2 AVDD2 AVDD2 GND GND GND GND AVDD2 AVDD2 AVDD2 GND F AVDD1 GND AVDD1 GND AVDD1 GND GND AVDD1 GND AVDD1 GND AVDD1 G GND AVDD1 GND AVDD1 GND GND GND GND AVDD1 GND AVDD1 GND H CLK– GND GND GND GND GND GND GND GND GND GND CSB J CLK+ GND CWQ+ GND CWI+ AVDD2 4LO+ GND GPO3 GPO1 PDWN SDIO K GND GND CWQ– GND CWI– AVDD2 4LO– RESET GPO2 GPO0 STBY SCLK L DRVDD DOUTH+ DOUTG+ DOUTF+ DOUTE+ DCO+ FCO+ DOUTD+ DOUTC+ DOUTB+ DOUTA+ DRVDD
04 0
M GND DOUTH– DOUTG– DOUTF– DOUTE– DCO– FCO– DOUTD– DOUTC– DOUTB– DOUTA– GND
3- 42 09 Figure 4. Pin Configuration
2 4 6 8 10 12 1 3 5 7 9 11 A B C D E F G H J K L M
05 0 3-
TOP VIEW
42
(Not to Scale)
09 Figure 5. Rev. 0 | Page 10 of 44 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS ULTRASOUND THEORY OF OPERATION CHANNEL OVERVIEW TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise Input Overdrive Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Recommendations Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE