Datasheet AD9279 (Analog Devices) - 5

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AD9279 Parameter1 T est Conditions/Comments Min Typ Max Unit
Input-Referred Noise Voltage RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB 1.5 nV/√Hz LNA gain = 17.9 dB 1.4 nV/√Hz LNA gain = 21.3 dB 1.3 nV/√Hz Noise Figure RS = 50 Ω, RFB = ∞ LNA gain = 15.6 dB 5.7 dB LNA gain = 17.9 dB 5.3 dB LNA gain = 21.3 dB 4.8 dB Input-Referred Dynamic Range RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB 164 dBFS/√Hz LNA gain = 17.9 dB 162 dBFS/√Hz LNA gain = 21.3 dB 160 dBFS/√Hz Output-Referred SNR −3 dBFS input, fRF = 2.5 MHz, f4LO = 155 dBc/√Hz 10 MHz, 1 kHz offset Two-Tone Intermodulation (IMD3) fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, −58 dB f4LO = 20 MHz, ARF1 = −1 dBFS, ARF2 = −21 dBFS, IMD3 relative to ARF2 Quadrature Phase Error I to Q, all phases, 1 σ 0.15 Degrees I/Q Amplitude Imbalance I to Q, all phases, 1 σ 0.015 dB Channel-to-Channel Matching Phase I to I, Q to Q, 1 σ 0.5 Degrees Amplitude I to I, Q to Q, 1 σ 0.25 dB POWER SUPPLY, MODE I/II/III AVDD1 1.7 1.8 1.9 V AVDD23 2.7 3.0 3.6 V DRVDD 1.7 1.8 1.9 V IAVDD1 TGC mode 197/270/328 mA CW Doppler mode 32 mA IAVDD2 TGC mode, no signal 240 mA CW Doppler mode 144 mA IDRVDD ANSI-644 mode 49/51/52 mA Low power (IEEE 1596.3 similar) mode 33/35/36 Total Power Dissipation TGC mode, no signal 1134/1269/ 1275/1410/ mW (Including Output Drivers) 1375 1594 CW Doppler mode 495 mW Power-Down Dissipation 5 mW Standby Power Dissipation 542 mW Power Supply Rejection Ratio 1.6 mV/V (PSRR) ADC RESOLUTION 12 Bits ADC REFERENCE Output Voltage Error VREF = 1 V ±50 mV Load Regulation at 1.0 mA VREF = 1 V 2 mV Input Resistance 6 kΩ 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 The overrange condition is specified as 6 dB more than the full-scale input range. 3 When the LNA gain is set to 15.6 dB, AVDD2 >3.0 V. Rev. 0 | Page 5 of 44 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS ULTRASOUND THEORY OF OPERATION CHANNEL OVERVIEW TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise Input Overdrive Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Recommendations Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE