Datasheet AD9671 (Analog Devices)

JESD204B Octal Ultrasound AFE with Digital Demodulator Data Sheet AD9671 FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, AAF, ADC, and digital demodulator/
The AD9671 is designed for low cost, low power, small size, and
decimator
ease of use for medical ultrasound applications. It contains eight
Low power: 150 mW per channel, time gain compensation
channels of a VGA with an LNA, a CW harmonic rejection I/Q
(TGC) mode, 40 MSPS
demodulator with programmable phase rotation, an AAF, an
62.5 mW per channel, continuous wave (CW) mode;
ADC, and a digital demodulator and decimator for data
<30 mW in power-down mode
processing and bandwidth reduction.
10 mm × 10 mm, 144-ball CSP_BGA TGC channel input referred noise: 0.82 nV/√Hz,
Each channel features a maximum gain of up to 52 dB, a fully
maximum gain
differential signal path, and an active input preamplifier termination.
Flexible power-down modes
The channel is optimized for high dynamic performance and
Fast recovery from low power standby mode: <2 μs
low power in applications where a small package size is critical.
Low noise preamplifier (LNA)
The LNA has a single-ended to differential gain that is selectable
Input referred noise: 0.78 nV/√Hz, gain = 21.6 dB
through the serial port interface (SPI). Assuming a 15 MHz noise
Programmable gain: 15.6 dB/17.9 dB/21.6 dB
bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR
0.1 dB compression: 1000 mV p-p/750 mV p-p/450 mV p-p
is 94 dB. In CW Doppler mode, each LNA output drives an I/Q
Flexible active input impedance matching
demodulator that has independently programmable phase
Variable gain amplifier (VGA)
rotation with 16 phase settings.
Attenuator range: 45 dB, linear-in-dB gain control
Power-down of individual channels is supported to increase
Postamplifier (PGA) gain: 21 dB/24 dB/27 dB/30 dB
battery life for portable applications. Standby mode allows quick
Antialiasing filter (AAF)
power-up for power cycling. In CW Doppler operation, the
Programmable, second-order low-pass filter (LPF) from
VGA, AAF, and ADC are powered down. The ADC contains
8 MHz to 18 MHz or 13.5 MHz to 30 MHz and high-pass
several features designed to maximize flexibility and minimize
filter (HPF)
system cost, such as a programmable clock, data alignment, and
Analog-to-digital converter (ADC)
programmable digital test pattern generation. The digital test
Signal-to-noise ratio (SNR): 75 dB, 14 bits up to 125 MSPS
patterns include built-in fixed patterns, built-in pseudorandom
JESD204B Subclass 0 coded serial digital outputs
patterns, and custom user defined test patterns entered via the SPI.
CW Doppler (CWD) mode harmonic rejection I/Q demodulator Individual programmable phase rotation Dynamic range per channel: 160 dBFS/√Hz Close-in SNR: 156 dBc/√Hz, 1 kHz offset, −3 dBFS input Digital demodulator/decimator I/Q demodulator with programmable oscillator APPLICATIONS Medical imaging/ultrasound Nondestructive testing (NDT) Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS CLK±, TX_TRIG± Synchronization Timing Diagram CW Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control DIGITAL OUTPUTS AND TIMING JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Converter and Lane Configuration Configure the Tail Bits and Control Bits Set Lane Identification Values Set Number of Frames per Multiframe, K Enable Scramble, SCR Set Lane Synchronization Options Verify FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Super Frame and Output Zero Stuffing Digital Outputs and Timing Preemphasis Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin GPOx Pins ADDRx Pins TX_TRIG± Pins ANALOG TEST TONE GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED START-UP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Update (Register 0x0FF) Profile Index and Software TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE