Datasheet AD9671 (Analog Devices) - 5

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Data Sheet AD9671 Parameter1 Test Conditions/Comments Min Typ Max Unit
Noise Figure Active Termination Matched LNA gain = 15.6 dB, RFB = 150 Ω 5.6 dB LNA gain = 17.9 dB, RFB = 200 Ω 4.8 dB LNA gain = 21.6 dB, RFB = 300 Ω 3.8 dB Unterminated LNA gain = 15.6 dB, RFB = ∞ 3.2 dB LNA gain = 17.9 dB, RFB = ∞ 2.9 dB LNA gain = 21.6 dB, RFB = ∞ 2.6 dB Correlated Noise Ratio No signal, correlated/uncorrelated −30 dB Output Offset −125 +125 LSB Signal-to-Noise Ratio (SNR) fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V 69 dBFS fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V 59 dBFS Close-In SNR fIN = 3.5 MHz at −0.5 dBFS, VGAIN = 0 V, −130 dBc/√Hz 1 kHz offset Second Harmonic fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V −70 dBc fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V −62 dBc Third Harmonic fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V −61 dBc fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V −55 dBc Two-Tone Intermodulation fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, −54 dBc Distortion (IMD3) ARF1 = −1 dBFS, ARF2 = −21 dBFS, VGAIN = 1.6 V, IMD3 relative to ARF2 Channel-to-Channel Crosstalk fIN1 = 5.0 MHz at −1 dBFS −60 dB Overrange condition2 −55 dB GAIN ACCURACY TA = 25°C Gain Law Conformance Error −1.6 < VGAIN < −1.28 V 0.4 dB −1.28 V < VGAIN < +1.28 V −1.3 +1.3 dB 1.28 V < VGAIN < 1.6 V −0.5 dB VGAIN = 0 V, normalized for ideal AAF −0.9 +0.9 dB loss Channel-to-Channel Matching −1.28 V < VGAIN < +1.28 V, 1 σ 0.1 dB PGA Gain 21/24/27/30 dB GAIN CONTROL INTERFACE Control Range Differential −1.6 +1.6 V Control Common Mode GAIN+, GAIN− 0.7 0.8 0.9 V Input Impedance GAIN+, GAIN− 10 MΩ Gain Range 45 dB Gain Sensitivity Analog 14 dB/V Digital step size 3.5 dB Response Time Analog 45 dB change 750 ns CW DOPPLER MODE LO Frequency fLO = fMLO/M 1 10 MHz Phase Resolution Per channel, 4LO3 mode 45 Degrees Per channel, 8LO3 mode, 16LO3 mode 22.5 Degrees Output DC Bias (Single-Ended) CWI+, CWI−, CWQ+, CWQ− AVDD2/2 V Output AC Current Range Per CWI+, CWI−, CWQ+, CWQ−, each ±2.2 ±2.5 mA channel enabled (2 fLO and baseband signal) Transconductance (Differential) Demodulated IOUT/VIN, per CWI+, CWI−, CWQ+, CWQ− LNA gain = 15.6 dB 3.3 mA/V LNA gain = 17.9 dB 4.3 mA/V LNA gain = 21.6 dB 6.6 mA/V Input Referred Noise Voltage RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB 1.6 nV/√Hz LNA gain = 17.9 dB 1.3 nV/√Hz LNA gain = 21.6 dB 1.0 nV/√Hz Rev. A| Page 5 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS CLK±, TX_TRIG± Synchronization Timing Diagram CW Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control DIGITAL OUTPUTS AND TIMING JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Converter and Lane Configuration Configure the Tail Bits and Control Bits Set Lane Identification Values Set Number of Frames per Multiframe, K Enable Scramble, SCR Set Lane Synchronization Options Verify FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Super Frame and Output Zero Stuffing Digital Outputs and Timing Preemphasis Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin GPOx Pins ADDRx Pins TX_TRIG± Pins ANALOG TEST TONE GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED START-UP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Update (Register 0x0FF) Profile Index and Software TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE