Datasheet AD7924-KGD (Analog Devices) - 3
| Fabricante | Analog Devices |
| Descripción | 4-Channel, 1 MSPS, 12-Bit A/D Converter with Sequencer in 16-Lead TSSOP |
| Páginas / Página | 8 / 3 — Known Good Die. AD7924-KGD. SPECIFICATIONS. Table 1. Parameter. Min. Typ … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 220 Kb |
| Idioma del documento | Inglés |
Known Good Die. AD7924-KGD. SPECIFICATIONS. Table 1. Parameter. Min. Typ Max. Unit. Test Conditions/Comments
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Known Good Die AD7924-KGD SPECIFICATIONS
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Temperature range is −40°C to +85°C.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz Signal-to-(Noise + Distortion), SINAD 70 dB @ 5 V 69 dB @ 3 V, typically 69.5 dB Signal-to-Noise Ratio, SNR 70 dB Total Harmonic Distortion, THD −77 dB @ 5 V, typically −84 dB −73 dB @ 3 V, typically −77 dB Peak Harmonic or Spurious Noise, SFDR −78 dB @ 5 V, typically −86 dB Intermodulation Distortion, IMD fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB Third-Order Terms −90 dB Aperture Delay 10 ns Aperture Jitter 50 ps Channel-to-Channel Isolation −85 dB fIN = 400 kHz Full Power Bandwidth 8.2 MHz @ 3 dB 1.6 MHz @ 0.1 dB DC ACCURACY Resolution 12 Bits Integral Nonlinearity, INL ±1 LSB Differential Nonlinearity, DNL −0.9/+1.5 LSB Guaranteed no missed codes to 12 bits 0 V to REFIN Input Range Straight binary output coding Offset Error ±8 LSB Typically ±0.5 LSB Offset Error Match ±0.5 LSB Gain Error ±1.5 LSB Gain Error Match ±0.5 LSB 0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos complement output coding Positive Gain Error ±1.5 LSB Positive Gain Error Match ±0.5 LSB Zero Code Error ±8 LSB Typically ±0.8 LSB Zero Code Error Match ±0.5 LSB Negative Gain Error ±1 LSB Negative Gain Error Match ±0.5 LSB ANALOG INPUT Input Voltage Range 0 REFIN V RANGE bit set to 1 0 2 × REFIN V RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V DC Leakage Current ±1 μA Input Capacitance 20 pF REFERENCE INPUT REFIN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA REFIN Input Impedance 36 kΩ fSAMPLE = 1 MSPS LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V Input Low Voltage, VINL 0.3 × VDRIVE V Input Current, IIN ±1 μA Typically 10 nA, VIN = 0 V or VDRIVE Input Capacitance, C 1 IN 10 pF Rev. A | Page 3 of 8 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE
Known Good Die AD7924-KGD SPECIFICATIONS
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Temperature range is −40°C to +85°C.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz Signal-to-(Noise + Distortion), SINAD 70 dB @ 5 V 69 dB @ 3 V, typically 69.5 dB Signal-to-Noise Ratio, SNR 70 dB Total Harmonic Distortion, THD −77 dB @ 5 V, typically −84 dB −73 dB @ 3 V, typically −77 dB Peak Harmonic or Spurious Noise, SFDR −78 dB @ 5 V, typically −86 dB Intermodulation Distortion, IMD fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB Third-Order Terms −90 dB Aperture Delay 10 ns Aperture Jitter 50 ps Channel-to-Channel Isolation −85 dB fIN = 400 kHz Full Power Bandwidth 8.2 MHz @ 3 dB 1.6 MHz @ 0.1 dB DC ACCURACY Resolution 12 Bits Integral Nonlinearity, INL ±1 LSB Differential Nonlinearity, DNL −0.9/+1.5 LSB Guaranteed no missed codes to 12 bits 0 V to REFIN Input Range Straight binary output coding Offset Error ±8 LSB Typically ±0.5 LSB Offset Error Match ±0.5 LSB Gain Error ±1.5 LSB Gain Error Match ±0.5 LSB 0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos complement output coding Positive Gain Error ±1.5 LSB Positive Gain Error Match ±0.5 LSB Zero Code Error ±8 LSB Typically ±0.8 LSB Zero Code Error Match ±0.5 LSB Negative Gain Error ±1 LSB Negative Gain Error Match ±0.5 LSB ANALOG INPUT Input Voltage Range 0 REFIN V RANGE bit set to 1 0 2 × REFIN V RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V DC Leakage Current ±1 μA Input Capacitance 20 pF REFERENCE INPUT REFIN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA REFIN Input Impedance 36 kΩ fSAMPLE = 1 MSPS LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V Input Low Voltage, VINL 0.3 × VDRIVE V Input Current, IIN ±1 μA Typically 10 nA, VIN = 0 V or VDRIVE Input Capacitance, C 1 IN 10 pF Rev. A | Page 3 of 8 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE